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1. 发明专利

JP2013197554A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013197554A
公开(公告)日：2013-09-30
申请号：JP2012066452
申请日：2012-03-23
申请人： Toshiba Corp , 株式会社東芝
发明人： KATO KAZUHIRO , IKIMURA TAKEHITO
IPC分类号： H01L21/822 , H01L27/04 , H01L27/06
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which inhibits deterioration of a signal supplied to an input/output terminal.SOLUTION: A semiconductor device comprises an NMOS transistor and a PMOS transistor. The NMOS transistor is connected between a first power terminal to which a first power supply voltage is applied and an input/output terminal to or from which an input/output signal is input or output. The PMOS transistor is connected between a second power terminal to which a second power supply voltage smaller then the first power supply voltage is applied and the input/output terminal. A gate of the NMOS transistor is connected to the second power terminal. A gate of the PMOS transistor is connected to the first power terminal.
摘要翻译：要解决的问题：提供一种抑制提供给输入/输出端子的信号劣化的半导体器件。解决方案：半导体器件包括NMOS晶体管和PMOS晶体管。 NMOS晶体管连接在施加了第一电源电压的第一电源端子和输入/输出信号被输入或输出的输入/输出端子之间。 PMOS晶体管连接在第二电源端子与施加第一电源电压的第二电源电压和输入/输出端子之间。 NMOS晶体管的栅极连接到第二电源端子。 PMOS晶体管的栅极连接到第一电源端子。

2. 发明专利

JP2012222280A Semiconductor device and dc-dc converter 有权
标题翻译：半导体器件和直流 - 直流转换器
公开(公告)号：JP2012222280A
公开(公告)日：2012-11-12
申请号：JP2011089083
申请日：2011-04-13
申请人： Toshiba Corp , 株式会社東芝
发明人： IKIMURA TAKEHITO
IPC分类号： H01L27/06 , H01L21/822 , H01L27/04
CPC分类号： H01L27/0259 , H02M3/155
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a DC-DC converter having high durability.SOLUTION: A semiconductor device comprises: first wiring for connecting high-potential-side power source potential; second wiring different from the first wiring for connecting the high-potential-side power source potential; a switching transistor whose one end is connected to the first wiring and whose other end is connected to an output terminal; and a protective element that is connected in parallel to the switching transistor between the high-potential-side power source potential and low-potential-side power source potential. The protective element includes: a first p-type semiconductor region that is connected to the first wiring; an n-type semiconductor region that is connected to the second wiring and contacts the first p-type semiconductor region; and a second p-type semiconductor region that contacts the n-type semiconductor region, is spaced apart from the first p-type semiconductor region, and is connected to wiring for connecting the low-potential-side power source potential.
摘要翻译：要解决的问题：提供具有高耐久性的半导体器件和DC-DC转换器。解决方案：半导体器件包括：用于连接高电位侧电源电位的第一布线; 与用于连接高电位侧电源电位的第一布线不同的第二布线; 开关晶体管，其一端连接到第一布线，另一端连接到输出端; 以及与高电位侧电源电位和低电位侧电源电位之间的开关晶体管并联连接的保护元件。保护元件包括：与第一布线连接的第一p型半导体区域; n型半导体区域，其连接到所述第二布线并接触所述第一p型半导体区域; 和与n型半导体区域接触的第二p型半导体区域与第一p型半导体区域间隔开，并且连接到用于连接低电位侧电源电位的布线。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2012015354A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2012015354A
公开(公告)日：2012-01-19
申请号：JP2010151007
申请日：2010-07-01
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAMURA YUKI , IKIMURA TAKEHITO
IPC分类号： H01L27/06 , H01L21/8234 , H01L29/78 , H01L29/786 , H01L29/861
CPC分类号： H01L27/0629
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which a MOS structure is used as a diode, with a low leakage current to a semiconductor substrate.SOLUTION: A semiconductor device comprises a field-effect transistor and a resistance element 20. The resistance element is connected between a gate electrode 19 of the field-effect transistor and a connection point 23 of a back gate electrode 24 and a first source/drain region 16 of the field-effect transistor. A voltage is applied between a second source/drain region 15 and the gate electrode 19.
摘要翻译：要解决的问题：提供一种半导体器件，其中使用MOS结构作为二极管，对半导体衬底具有低的漏电流。解决方案：半导体器件包括场效应晶体管和电阻元件20.电阻元件连接在场效应晶体管的栅电极19和背栅电极24的连接点23和第一场效应晶体管的源极/漏极区域16。在第二源极/漏极区域15和栅极电极19之间施加电压。版权所有：（C）2012，JPO＆INPIT

4. 发明专利

JP2009032968A Semiconductor device, and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009032968A
公开(公告)日：2009-02-12
申请号：JP2007196360
申请日：2007-07-27
申请人： Toshiba Corp , 株式会社東芝
发明人： IKIMURA TAKEHITO
IPC分类号： H01L27/06 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/088 , H01L29/78 , H01L29/861
摘要： PROBLEM TO BE SOLVED: To provide a structure of a semiconductor device for making constant a difference between the breakdown voltages of an LDMOS transistor and a protection diode at all times, and to provide a manufacturing method thereof.
SOLUTION: On a semiconductor substrate 1, an LDMOS is formed and a diode for protecting the LDMOS from electrostatic breakdown is formed. The drain region 5 of the LDMOS is used as the cathode region 11 of the diode, and the back gate region of the LDMOS is used as the anode region 14 of the diode. The cathode region 11 of the diode and the drain region 5 of the LDMOS are formed in the same process, and the anode 14 of the diode and the back gate region 4 of the LDMOS are formed in the same process. The difference between the breakdown voltages of the lateral MOS transistor in which the source region and the drain region are arranged in the lateral direction of the semiconductor substrate and the protection diode is made constant at all times.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供一直使LDMOS晶体管和保护二极管的击穿电压之间始终不变的半导体器件的结构，并提供其制造方法。解决方案：在半导体衬底1上形成LDMOS，并形成用于保护LDMOS免受静电击穿的二极管。 LDMOS的漏极区域5用作二极管的阴极区域11，并且LDMOS的背栅极区域用作二极管的阳极区域14。二极管的阴极区域11和LDMOS的漏极区域5以相同的工艺形成，二极管的阳极14和LDMOS的背栅极区域4以相同的工艺形成。其中源极区域和漏极区域在半导体衬底和保护二极管的横向方向上布置的横向MOS晶体管的击穿电压之间的差异始终保持恒定。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2015002510A 静電気保護回路审中-公开
标题翻译：静电保护电路
公开(公告)号：JP2015002510A
公开(公告)日：2015-01-05
申请号：JP2013127366
申请日：2013-06-18
申请人：株式会社東芝 , Toshiba Corp
发明人： IKIMURA TAKEHITO
IPC分类号： H03K17/16 , H01L21/822 , H01L27/04 , H01L27/06 , H02H7/20 , H02H9/04
CPC分类号： H02H9/046
摘要：【課題】電源電圧の揺動に対する誤動作を抑制する静電気保護回路を提供することを目的とする。【解決手段】高電位側の第1の電源ライン10と、低電位側の第2の電源ライン11と、第1の接続ノード12を有する。第1の電源ライン10と第1の接続ノード12間には、所定の閾値電圧で電流が急激に増加するクランプ回路3が接続される。第1の接続ノード12と第2の電源ライン11間には、クランプ回路3の電流の変化に応答してトリガ信号を出力するトリガ回路4が接続される。第1の接続ノード12と第2の電源ライン11間の電圧でバイアスされるバッファ回路5は、トリガ回路4のトリガ信号に応答して駆動信号を出力する。第1の電源ライン10と第2の電源ライン11間には、前記バッファ回路5の駆動信号に応じてオン/オフするスイッチ回路6が接続される。【選択図】図1
摘要翻译：要解决的问题：提供一种在存在电源电压波动的情况下抑制故障的静电保护电路。解决方案：静电保护电路具有高电位侧的第一电力线10，低电位侧和第一连接节点12.被配置为允许在预定阈值电压下的电流突然增加的钳位电路3连接在第一电力线10和第一连接节点12之间。触发电路4用于输出响应于通过钳位电路3的电流变化的触发信号连接在第一连接节点12和第二电力线11之间。由第一连接节点12和第二电力线11之间的电压偏置的缓冲电路5输出一个响应于触发电路4的触发信号，驱动信号。响应于缓冲电路5的驱动信号，开关电路6接通/断开，是conn 在第一电力线10和第二电力线11之间。

6. 发明专利

JP2012124207A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2012124207A
公开(公告)日：2012-06-28
申请号：JP2010271419
申请日：2010-12-06
申请人： Toshiba Corp , 株式会社東芝
发明人： IKIMURA TAKEHITO , AKIMOTO RIEKO , WATANABE KIMINORI , SHIRAI KOJI , FUKAI YASUSHI
IPC分类号： H01L27/08 , H01L21/336 , H01L21/76 , H01L21/822 , H01L27/04 , H01L29/78
CPC分类号： H01L29/7322 , H01L27/0623 , H01L29/0653 , H01L29/0878 , H01L29/7816
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing malfunction of other elements mounted on the same substrate in a mixed manner.SOLUTION: A semiconductor device comprises a p-type semiconductor layer 12, an n-type source region 13, an insulator 23, an n-type semiconductor region 20, an n-type drain region 14, a p-type channel region 12a, a gate insulating film 15, a gate electrode 16, a source electrode 18, a drain electrode 19, and an electrode 21. The insulator is provided in a trench t1 formed so as to extend in the thickness direction of the p-type semiconductor layer from a surface of the p-type semiconductor layer. The n-type semiconductor region is provided in the surface of the p-type semiconductor layer between the drain region and the insulator. The electrode is connected to the n-type semiconductor region.
摘要翻译：要解决的问题：提供能够以混合方式防止安装在同一基板上的其它元件的故障的半导体器件。解决方案：半导体器件包括p型半导体层12，n型源极区13，绝缘体23，n型半导体区20，n型漏极区14，p型沟道区域12a，栅极绝缘膜15，栅极电极16，源电极18，漏极电极19和电极21.绝缘体设置在沟槽t1中，其形成为沿着p- 从p型半导体层的表面形成半导体层。 n型半导体区域设置在漏极区域和绝缘体之间的p型半导体层的表面。电极连接到n型半导体区域。版权所有（C）2012，JPO＆INPIT

7. 发明专利

JP2014086580A Protection circuit 审中-公开
标题翻译：保护电路
公开(公告)号：JP2014086580A
公开(公告)日：2014-05-12
申请号：JP2012234621
申请日：2012-10-24
申请人： Toshiba Corp , 株式会社東芝
发明人： KATO KAZUHIRO , IKIMURA TAKEHITO
IPC分类号： H01L27/04 , H01L21/822 , H01L27/06 , H03K17/08
CPC分类号： H02H9/046
摘要： PROBLEM TO BE SOLVED: To provide a protection circuit capable of protecting against ESD and such and capable of avoiding excessive lowering of power supply voltage during a protective operation.SOLUTION: A control circuit is coupled between power terminals. The control circuit outputs a control signal when a voltage between the power terminals exceeds a predetermined value caused by a surge and such. A voltage clamp element having a PN junction to which a reverse bias is applied by a power supply voltage between the power terminals serially coupled to an output current path of a shunt transistor whose conduction state is controlled by the control signal.
摘要翻译：要解决的问题：提供能够防止ESD等的保护电路，并且能够避免在保护操作期间电源电压的过度降低。解决方案：控制电路耦合在电源端子之间。当电源端子之间的电压超过由浪涌引起的预定值时，控制电路输出控制信号。具有PN结的电压钳位元件，通过在与控制信号控制其导通状态的分流晶体管的输出电流路径串联耦合的电源端子之间的电源电压施加反向偏压。

8. 发明专利

JP2014038889A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2014038889A
公开(公告)日：2014-02-27
申请号：JP2012178948
申请日：2012-08-10
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIRAI KOJI , IKIMURA TAKEHITO , WATANABE KIMINORI
IPC分类号： H01L21/336 , H01L21/822 , H01L21/8234 , H01L21/8238 , H01L27/04 , H01L27/088 , H01L27/092 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having high resistance against surge current.SOLUTION: A semiconductor device according to an embodiment comprises: a first conductivity type first semiconductor layer; a second conductivity type second semiconductor layer provided on a part of the first semiconductor layer; a first conductivity type third semiconductor layer and a second conductivity type fourth semiconductor layer having an effective impurity concentration higher than an effective impurity concentration of the second semiconductor layer, which are provided on a part of the second semiconductor layer and alternately arranged along a first direction; a gate insulation film provided on the second semiconductor layer; and a gate electrode provided on the gate insulation film. A resistance value between a boundary face with the first semiconductor layer and a boundary face with the third semiconductor layer, which is a resistance value of the second semiconductor layer in a second direction orthogonal to the first direction is larger than a resistance value between a position corresponding to a midpoint of the third semiconductor layer and a position corresponding to a midpoint of the fourth semiconductor layer, which is a resistance value of the second semiconductor layer in the first direction.
摘要翻译：要解决的问题：提供具有高抗冲击电流的半导体器件。解决方案：根据实施例的半导体器件包括：第一导电类型的第一半导体层; 设置在第一半导体层的一部分上的第二导电类型的第二半导体层; 第一导电型第三半导体层和第二导电型第四半导体层，其具有比第二半导体层的有效杂质浓度高的有效杂质浓度，其设置在第二半导体层的一部分上，并沿着第一方向 ; 设置在所述第二半导体层上的栅极绝缘膜; 以及设置在栅极绝缘膜上的栅电极。在与第一半导体层的边界面和与第三半导体层的边界面之间的电阻值是与第一方向正交的第二方向上的第二半导体层的电阻值的电阻值大于位置对应于第三半导体层的中点和与第四半导体层的中点对应的位置，该第四半导体层是第一半导体层的第一方向的电阻值。

9. 发明专利

JP2013197128A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2013197128A
公开(公告)日：2013-09-30
申请号：JP2012059591
申请日：2012-03-16
申请人： Toshiba Corp , 株式会社東芝
发明人： KATO KAZUHIRO , TSURUMI HIROYUKI , SATO YUKIO , IKIMURA TAKEHITO , KUMAMOTO AKIRA , YAMAMOTO HIROYUKI , IMAKAKE SHOICHI , ASAKAWA TORU
IPC分类号： H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/06 , H01L27/092
CPC分类号： H02H3/08 , H01L27/0255 , H02H9/041
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing a circuit area.SOLUTION: In a semiconductor device, a first resistor has one end connected to a first power supply terminal to which a first power supply voltage is applied. A capacitor is connected between the other end of the first resistor and a second power supply terminal to which a second power supply voltage is applied. A first transistor has a source connected to the first power supply terminal, and a gate connected to a connection point between the first resistor and the capacitor. A second resistor is connected between a drain of the first transistor and the second power supply terminal. A first diode is connected between the gate and the source of the first transistor and in a reverse direction to a polarity of a voltage generated at the first resistor. A second transistor has a drain connected to the first power supply terminal, a source connected to the second power supply terminal, and a gate driven by an output of the first transistor. A second diode is connected between the gate and the source of the second transistor and in a reverse direction to a polarity of a voltage generated at the second resistor.
摘要翻译：要解决的问题：提供能够减小电路面积的半导体器件。解决方案：在半导体器件中，第一电阻器的一端连接到施加有第一电源电压的第一电源端子。电容器连接在第一电阻器的另一端和施加第二电源电压的第二电源端子之间。第一晶体管具有连接到第一电源端子的源极和连接到第一电阻器和电容器之间的连接点的栅极。第二电阻器连接在第一晶体管的漏极和第二电源端子之间。第一二极管连接在第一晶体管的栅极和源极之间，并且与第一电阻器产生的电压的极性相反。第二晶体管具有连接到第一电源端子的漏极，连接到第二电源端子的源极和由第一晶体管的输出驱动的栅极。第二二极管连接在第二晶体管的栅极和源极之间，并且与第二电阻器产生的电压的极性相反。

10. 发明专利

JPH08274032A VAPOR GROWTH DEVICE 失效
公开(公告)号：JPH08274032A
公开(公告)日：1996-10-18
申请号：JP7433295
申请日：1995-03-31
申请人： TOSHIBA CORP
发明人： IKIMURA TAKEHITO
IPC分类号： H01L21/683 , H01L21/205 , H01L21/68
摘要： PURPOSE: To reduce the dispersion in film thickness in the horizontal direction of the film formed on a substrate surface by a method wherein flange the protrusions are provided on the boundaries of plural planes of the susceptor cylindrically formed comprising plural planes for mounting semiconductor substrates. CONSTITUTION: The inside of a reaction tube 11 is provided with a susceptor 12 and a hanging jig 13 for transmitting rotary motion to the susceptor 12. The substrates 15 are mounted on circular back facings 16 on the surface of the susceptor 12. The flange protrusions 21 are provided on the boundaries of the surfaces comprising the susceptor 12. In such a constitution, the growing gas and carrier gas injected from gas injecting parts 14 are reacted and to be given the ratary motion during the step so that the gasses may become an even current on the surfaces of the substrates 15 mounted on the surfaces comprising the susceptor 12 thereby making the gas flow rate almost even in the end parts and the central parts of the substrates 15. Accordingly, the films in the less dispersion in the vertical and horizontal directions of the substrates 15 can be formed.

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