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    • 2. 发明专利
    • Semiconductor device and manufacturing method of the same
    • 半导体器件及其制造方法
    • JP2012160579A
    • 2012-08-23
    • JP2011019282
    • 2011-01-31
    • Toshiba Corp株式会社東芝
    • HONDA TOMOKOIGUCHI TOMOHIROFUKUMITSU MASAKOHONDA SATOSHI
    • H01L23/28H01L23/00
    • H01L24/97H01L21/561H01L21/568H01L23/552H01L24/73H01L2224/32225H01L2224/48091H01L2224/48227H01L2224/73265H01L2224/97H01L2924/15311H01L2924/181H01L2924/1815H01L2924/00012H01L2224/85H01L2224/83H01L2924/00H01L2924/00014
    • PROBLEM TO BE SOLVED: To provide a semiconductor device which increases a connection area between a conductive shield layer and ground wiring and thereby improving the reliability.SOLUTION: A semiconductor device 1 includes: a circuit board 10 having an insulation substrate 11, multiple first wiring layers provided on a first main surface of the insulation substrate, multiple second wiring layers provided on a second main surface of the insulation substrate, and multiple vias 14 penetrating from the first main surface of the insulation substrate to a lower surface thereof; a semiconductor element 20 mounted on the first main surface of the insulation substrate in the circuit board; a sealing resin layer 30 sealing the semiconductor element; and a conductive shield layer 40 covering the sealing resin layer. Any of the multiple first wiring layers are exposed at the end part side of the circuit board, and the conductive shield layer extends toward the semiconductor element and gets into the sealing resin layer to electrically connect with the first wiring layer exposed at the end part side of the circuit board.
    • 要解决的问题:提供一种增加导电屏蔽层和接地布线之间的连接区域并从而提高可靠性的半导体器件。 解决方案:半导体器件1包括:具有绝缘基板11的电路板10,设置在绝缘基板的第一主表面上的多个第一布线层,设置在绝缘基板的第二主表面上的多个第二布线层 ,多个通孔14从绝缘基板的第一主表面贯穿其下表面; 安装在电路板中的绝缘基板的第一主表面上的半导体元件20; 密封半导体元件的密封树脂层30; 以及覆盖密封树脂层的导电屏蔽层40。 多个第一布线层中的任一个在电路板的端部侧露出,并且导电屏蔽层朝向半导体元件延伸并进入密封树脂层,以与在端部侧暴露的第一布线层电连接 的电路板。 版权所有(C)2012,JPO&INPIT
    • 3. 发明专利
    • Semiconductor device and manufacturing method of the same
    • 半导体器件及其制造方法
    • JP2012160576A
    • 2012-08-23
    • JP2011019271
    • 2011-01-31
    • Toshiba Corp株式会社東芝
    • IGUCHI TOMOHIROFUKUMITSU MASAKOHONDA SATOSHIHONDA TOMOKOYAMAMOTO KAZUICHI
    • H01L23/28H01L23/00H05K9/00
    • H01L23/552H01L24/73H01L24/97H01L2224/32225H01L2224/48091H01L2224/48227H01L2224/73265H01L2224/97H01L2924/15311H01L2924/1815H01L2924/19107H01L2224/83H01L2224/85H01L2924/00012H01L2924/00H01L2924/00014
    • PROBLEM TO BE SOLVED: To provide a semiconductor device which improves design flexibility of electric wiring.SOLUTION: A semiconductor device according to the embodiment includes: a circuit board having an insulation substrate, multiple wiring lines forming a first wiring layer provided at the upper surface side of the insulation substrate, multiple wiring lines forming a second wiring layer provided at the lower surface side of the insulation substrate, and multiple vias penetrating from an upper surface to a lower surface of the insulation substrate; a semiconductor element mounted on an upper surface of the circuit board; and a sealing resin layer sealing the semiconductor element and provided at the upper surface of the circuit board. Further, the semiconductor device includes: a conductive shield layer covering an upper surface of the sealing resin layer and a part of a side surface of the sealing resin layer; and a conductive member electrically connecting the conductive shield layer covering the part of the side surface of the sealing resin layer with at least one of the multiple wiring lines forming the first wiring layer.
    • 要解决的问题:提供一种提高电布线设计灵活性的半导体器件。 解决方案:根据实施例的半导体器件包括:具有绝缘基板的电路板,形成设置在绝缘基板的上表面侧的第一布线层的多条布线,形成设置有第二布线层的多条布线 在所述绝缘基板的下表面侧,从所述绝缘基板的上表面贯穿到所述绝缘基板的下表面的多个通孔; 安装在所述电路板的上表面上的半导体元件; 以及密封树脂层,密封半导体元件并设置在电路板的上表面。 此外,半导体器件包括:覆盖密封树脂层的上表面和密封树脂层的侧表面的一部分的导电屏蔽层; 以及导电构件,其将覆盖所述密封树脂层的侧面的所述一部分的所述导电性屏蔽层与形成所述第一布线层的所述多条布线中的至少一方电连接。 版权所有(C)2012,JPO&INPIT
    • 4. 发明专利
    • Surface mounting diode and method of manufacturing the same
    • 表面安装二极管及其制造方法
    • JP2011159761A
    • 2011-08-18
    • JP2010019681
    • 2010-01-29
    • Toshiba Corp株式会社東芝
    • KITANI TOMOYUKITOJO HIROSHIATAGI TAKAOHIGUCHI KAZUTOIGUCHI TOMOHIROFUKUMITSU MASAKOOBATA SUSUMUASANO YUSAKU
    • H01L21/329H01L23/48H01L29/861
    • H01L21/782H01L23/48H01L2924/0002H01L2924/00
    • PROBLEM TO BE SOLVED: To provide a semiconductor device, the polarities of which can be identified easily by appearance without causing tombstone, and to provide a method of manufacturing the semiconductor device. SOLUTION: A surface mounting diode includes: a diode chip 2 having a first main surface A1 and a second main surface A2 that face with each other; a cathode electrode 3 having an internal electrode part 3a provided on the first main surface A1 and an external electrode part 3b provided on a surface of the internal electrode part 3a; an anode electrode 4 having an internal electrode part 4a provided on a surface of the second main surface A2 and an external electrode part 4b provided on a surface of the internal electrode part 4a, wherein a thickness of the external electrode part 4b is the same as that of the external electrode part 3b of the cathode electrode; a first coating member 5 coating a peripheral surface of the internal electrode part 3a of one of either the cathode electrode and the anode electrode and a peripheral surface of the diode chip 2; and a second coating member 6 coating a peripheral surface of the internal electrode part 4a of the other of the cathode electrode and the anode electrode and having a color different from that of the first coating member 5. COPYRIGHT: (C)2011,JPO&INPIT
    • 要解决的问题:提供一种可以通过外观容易地识别其极性而不产生墓碑的半导体器件,并提供一种半导体器件的制造方法。 解决方案:表面安装二极管包括:具有彼此面对的第一主表面A1和第二主表面A2的二极管芯片2; 设置在第一主面A1上的内部电极部分3a和设置在内部电极部分3a的表面上的外部电极部分3b的阴极电极3; 设置在第二主面A2的表面上的内部电极部分4a和设置在内部电极部分4a的表面上的外部电极部分4b的阳极电极4,其中外部电极部分4b的厚度与 阴极电极的外部电极部分3b; 涂覆阴极电极和阳极电极之一的内部电极部分3a的外周表面和二极管芯片2的外围表面的第一涂覆部件5; 以及第二涂覆部件6,其涂覆阴极电极和阳极电极中的另一个的内部电极部分4a的周面,并且具有与第一涂覆部件5不同的颜色。版权所有(C)2011 ,JPO&INPIT
    • 5. 发明专利
    • Manufacturing method of semiconductor device and the semiconductor device
    • 半导体器件和半导体器件的制造方法
    • JP2012160577A
    • 2012-08-23
    • JP2011019272
    • 2011-01-31
    • Toshiba Corp株式会社東芝
    • FUKUMITSU MASAKOIGUCHI TOMOHIROHONDA TOMOKOHONDA SATOSHIYAMAMOTO KAZUICHI
    • H01L21/56H01L23/12H01L23/28
    • H01L24/97H01L24/73H01L2224/32225H01L2224/48091H01L2224/48227H01L2224/49171H01L2224/73265H01L2224/97H01L2924/15311H01L2924/16152H01L2924/181H01L2924/00014H01L2924/00012
    • PROBLEM TO BE SOLVED: To provide a manufacturing method which manufactures a more reliable semiconductor device.SOLUTION: In a manufacturing method of a semiconductor device according to the embodiment, a substrate, in which circuit boards having an insulation substrate, multiple first wiring layers, multiple second wiring layers and multiple vias are continuously provided, is prepared. Semiconductor elements are respectively mounted on the multiple circuit boards, and a sealing resin layer sealing the semiconductor elements and the multiple first wiring layers is formed on an upper surface of the substrate. A lower surface of the substrate is contacted with a ground and the sealing resin layer and the circuit boards are respectively singulated. Further, grooves are formed on the ground between the singulated circuit boards. An upper surface of the respective sealing resin layers are covered by a conductive shield layer and side surfaces of the respective sealing resin layers and at least parts of side surfaces of the respective circuit boards are covered by the conductive shield layer. The conductive shield layer is inserted into a space between the singulated circuit boards in a direction that proceeds from the sealing resin layer to the groove.
    • 要解决的问题:提供制造更可靠的半导体器件的制造方法。 解决方案:在根据实施例的半导体器件的制造方法中,准备连续提供具有绝缘基板的电路板,多个第一布线层,多个第二布线层和多​​个通孔的基板。 半导体元件分别安装在多个电路板上,并且在基板的上表面上形成密封半导体元件和多个第一布线层的密封树脂层。 基板的下表面与地面接触,并且密封树脂层和电路板分别被分割。 此外,在单个电路板之间的地面上形成凹槽。 各个密封树脂层的上表面被导电屏蔽层覆盖,并且各个密封树脂层的侧表面和各个电路板的至少一部分侧表面被导电屏蔽层覆盖。 导电屏蔽层沿着从密封树脂层前进到凹槽的方向插入在单电路板之间的空间中。 版权所有(C)2012,JPO&INPIT
    • 6. 发明专利
    • Semiconductor device and method of manufacturing semiconductor device
    • 半导体器件及制造半导体器件的方法
    • JP2011066346A
    • 2011-03-31
    • JP2009217884
    • 2009-09-18
    • Toshiba Corp株式会社東芝
    • IGUCHI TOMOHIROHIGUCHI KAZUTOKITANI TOMOYUKINISHIUCHI HIDEOFUKUMITSU MASAKOTOJO HIROSHIKATO KYOKO
    • H01L23/12
    • H01L2224/34H01L2224/37599H01L2224/37647H01L2224/8385H01L2924/00014H01L2924/00012
    • PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the semiconductor device, in which further reduction in size of the device and reduction of internal resistance are attained while the effects of manufacturing at low cost and improvement of manufacturing efficiency are maintained. SOLUTION: A semiconductor device comprises: a semiconductor element 2; a first wiring layer 3 connected with a first electrode 2a on a side of a first surface A1; a second wiring layer 4 connected with a second electrode 2b at a side of a second surface A2; an insulating layer 5 provided around the semiconductor element 2 excluding the first surface A1 and the second surface A2; a through-hole 6 passing through the side of the first surface A1 and the side of the second surface A2 in the insulating layer 5; a third wiring layer 7 provided at the side of the first surface A1 and connected with the second wiring layer 4; external electrodes 8 provided on the first wiring layer 3 and the third wiring layer 7 respectively; and an enclosure 9 sealing the side of the second surface A2 including the second wiring layer 4 and sealing the periphery of the external electrodes 8 excluding an area exposed at the side of the first surface A1, the semiconductor element 2, the first wiring layer 3, and the third wiring layer 7. COPYRIGHT: (C)2011,JPO&INPIT
    • 将要解决的问题:提供一种半导体器件和半导体器件的制造方法,其中,在制造成本低且制造性能提高的同时,实现器件尺寸的进一步减小和内阻的降低 保持效率。 解决方案:半导体器件包括:半导体元件2; 与第一面A1一侧的第一电极2a连接的第一布线层3; 与第二表面A2侧的第二电极2b连接的第二布线层4; 设置在除了第一面A1和第二面A2之外的半导体元件2周围的绝缘层5; 穿过绝缘层5中的第一表面A1侧和第二表面A2侧的通孔6; 设置在第一表面A1侧并与第二布线层4连接的第三布线层7; 设置在第一布线层3和第三布线层7上的外部电极8; 以及密封包括第二布线层4的第二表面A2的侧面并且密封外部电极8的外围的外壳9,除了暴露在第一表面A1,半导体元件2,第一布线层3 ,和第三布线层7.版权所有(C)2011,JPO&INPIT
    • 8. 发明专利
    • Semiconductor device and method of manufacturing semiconductor device
    • 半导体器件及制造半导体器件的方法
    • JP2010225951A
    • 2010-10-07
    • JP2009073047
    • 2009-03-25
    • Toshiba Corp株式会社東芝
    • NISHIUCHI HIDEOHIGUCHI KAZUTOKITANI TOMOYUKIIGUCHI TOMOHIROFUKUMITSU MASAKOTOJO HIROSHIKATO KYOKO
    • H01L23/12H01L21/3205H01L23/52
    • H01L24/97H01L2224/13
    • PROBLEM TO BE SOLVED: To provide a semiconductor device which has high insulation performance and high strength while maintaining such an effect as the miniaturization of the device, more reduction in the resistance of an internal resistance, manufacturing at low cost, and improvement in manufacturing efficiency, and a method of manufacturing the semiconductor device. SOLUTION: The device has a substrate 2 in which a source electrode S and a gate electrode G are prepared in a first surface S1, and a drain electrode D is prepared in a second surface S2, a first wiring layer 3 which is connected to the source electrode S prepared on the first surface S1, a second wiring layer 4 which is prepared on the first surface S1, and connected to the drain electrode D, copper posts 5 prepared on the first wiring layer 3 and on the second wiring layer 4, respectively, a third wiring layer 6 which is connected to the drain electrode D prepared on the second surface S2, a through-hole 7 which penetrates the substrate 2, and establishes conduction between the second wiring layer 4 and the third wiring layer 6, and an enclosure 9 in which only a first facing surface and a second facing surface of the copper post 5 are exposed, and the first wiring layer 3, the second wiring layer 4, the third wiring layer 6 and the substrate 2 are sealed. COPYRIGHT: (C)2011,JPO&INPIT
    • 要解决的问题:为了提供一种具有高绝缘性能和高强度的半导体器件,同时保持了器件的小型化的效果,内阻的电阻更多的降低,低成本的制造和改进 的制造效率,以及半导体装置的制造方法。 解决方案:器件具有在第一表面S1中制备源电极S和栅极电极G的衬底2,并且在第二表面S2中制备漏电极D,第一布线层3 连接到在第一表面S1上制备的源电极S,制备在第一表面S1上并连接到漏电极D的第二布线层4,在第一布线层3上准备的铜柱5和第二布线 层4分别连接到在第二表面S2上制备的漏电极D的第三布线层6,穿透基板2的通孔7,并且在第二布线层4和第三布线层之间建立导通 6以及仅露出铜柱5的第一面对面和第二面对面的壳体9,并且第一配线层3,第二配线层4,第三配线层6和基板2被密封 。 版权所有(C)2011,JPO&INPIT