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1. 发明专利

JP2001189449A LATERAL HIGH BREAKDOWN VOLTAGE TRANSISTOR 失效
公开(公告)号：JP2001189449A
公开(公告)日：2001-07-10
申请号：JP37156899
申请日：1999-12-27
申请人： TOSHIBA CORP
发明人： WATANABE KIMINORI , MATSUOKA KEISUKE , ITO TAKAO
IPC分类号： H01L29/78
摘要： PROBLEM TO BE SOLVED: To restrain a lateral parasitic bipolar transistor from being turned on, so as to provide a lateral high withstand voltage transistor which is set higher in breakdown strength. SOLUTION: An N--type drain region 2 and an N+-type source region 3 are formed in a P--type silicon substrate 1 separated from each other, a gate electrode 5 formed in a channel 4 insulated from the substrate 1, an N+-type drain contact region 6 formed in the drain region 2, a drain wiring 12 electrically connected to the drain region 2 via the drain contact region 6, a P+-type substrate contact region 7 formed in the source region 2 reaching the substrate 1, and a source wiring 13 electrically connected to the source region 3 and also to the substrate 1 through the intermediary of the substrate contact region 7. The substrate contact region 7 is extended, from the inside of a contact surface 15 of a source wiring 13 to the outside of the contact surface 15.

2. 发明专利

JPH08102540A CONDUCTIVE MODULATION TYPE MOSFET 失效
公开(公告)号：JPH08102540A
公开(公告)日：1996-04-16
申请号：JP24619595
申请日：1995-09-25
申请人： TOSHIBA CORP
发明人： WATANABE KIMINORI , YAMAGUCHI YOSHIHIRO , NAKAGAWA AKIO
IPC分类号： H01L29/78 , H01L29/739
摘要： PURPOSE: To provide a conductive modulation type MOSFET which can increase a latch-up current without raising an ON-voltage and can improve load short circuit strength. CONSTITUTION: When a width of a gate electrode 15 is LG and a width of a high resistance layer 13 held between a drain layer 11 and a base layer 17 is Wn in a conductive modulation type MOSFET, conditions of LG>=30μm and Wn >=120μm are satisfied.

3. 发明专利

JPH01315159A DIELECTRIC-ISOLATION SEMICONDUCTOR SUBSTRATE AND ITS MANUFACTURE 失效
公开(公告)号：JPH01315159A
公开(公告)日：1989-12-20
申请号：JP17370188
申请日：1988-07-14
申请人： TOSHIBA CORP
发明人： FURUKAWA KAZUYOSHI , FUKUDA KIYOSHI , TANZAWA KATSUJIRO , NAKAGAWA AKIO , YAMAGUCHI YOSHIHIRO , WATANABE KIMINORI
IPC分类号： H01L21/02 , H01L21/762 , H01L27/12
摘要： PURPOSE:To reduce a curvature by a method wherein a first silicon layer and a second silicon layer which is thicker than the layer are bonded by laying an oxide film between them, the first silicon layer is set to a plane orientation of (100) or (110) and the second silicon layer is set to a plane orientation of (111). CONSTITUTION:A first silicon substrate 1 is of an n-type; its plane orientation is (100); its thickness is 500mum; silicon oxide films 3 of 1mum are formed on its surfaces by thermal oxidation. A second silicon substrate 2 is set to a plane orientation of (111) and its thickness is 500mum. These two substrates 1, 2 are bonded directly; a united wafer 10 is obtained. then a second thick silicon layer to be used as a base is set to (111) and a first silicon layer to be used as an active layer is set to (100), a curvature is reduced as compared with a case where both the first silicon layer and the second silicon layer are set to a plane orientation of (100).

4. 发明专利

JPS63194361A HIGH BREAKDOWN VOLTAGE PLANAR TYPE SEMICONDUCTOR ELEMENT 失效
公开(公告)号：JPS63194361A
公开(公告)日：1988-08-11
申请号：JP2623587
申请日：1987-02-09
申请人： TOSHIBA CORP
发明人： WATANABE KIMINORI , NAKAGAWA AKIO
IPC分类号： H01L29/861 , H01L29/06
摘要： PURPOSE:To increase breakdown voltage by disposing a high resistance film onto a second conductivity type low-concentration diffusion layer and a high resistance substrate on the out side of the diffusion layer through an insulating film in a high breakdown-voltage planar type semiconductor element in which the second conductivity type low-concentration diffusion layer is formed, surrounding a second conductivity type high-concentration diffusion layer in the first conductivity type high resistance substrate. CONSTITUTION:A p type layer 2 in high impurity concentration is shaped to the surface of a high-resistance n type Si layer 1, and a p type layer 6 in low impurity concentration is formed around the layer 2. The total amount of an impurity per unit area at the time of viewing from the surface of the p type layer 6 is specified to 1-5.5X10 /cm . An n type layer 9 is shaped around an element separated at a fixed distance from the p type layer 6, and a semi-insulating polycrystalline silicon film 8 is disposed extending over the n type layer 9 from the p type layer 2 through an insulating film 7. When breakdown voltage of 70% of more is permitted at that time, the length of the p type layer 6 extends over 120mum or less when the total amount of the impurity in the p type layer exceeds 4X10 /cm . When the p layer is formed at two stages, however, the length of the layer in concentration exceeding 4X10 /cm may extend over 120mum or less.

5. 发明专利

JPS61198781A CONDUCTING MODULATION TYPE MOSFET 失效
公开(公告)号：JPS61198781A
公开(公告)日：1986-09-03
申请号：JP3925185
申请日：1985-02-28
申请人： TOSHIBA CORP
发明人： NAKAGAWA AKIO , WATANABE KIMINORI , YAMAGUCHI YOSHIHIRO , OHASHI HIROMICHI
IPC分类号： H01L29/78 , H01L29/06 , H01L29/739
摘要： PURPOSE:To prevent the latch up of a parasitic thyristor, by setting the current value, when a conducting modulation type MOSFET is latched up, larger than the current value when a channel region is saturated. CONSTITUTION:In an effective element region in a conducting modulation type MOSFET, parameters are set so as to satisfy (W.Sa)/T ], where W is the total channel width per unit area; Sa is a gate electrode area of a part, which has a conducting-type high-resistance layer directly beneath the gate within the same unit area; T is the total outer length of a base diffused layer within the same unit area; and the channel length l is made to be, e.g., 4mum or less. The saturated value of the element is made smaller than the latch-up current value, when a gate voltage is applied so that a ratio Va/D between the gate voltage Va and the thickness (d) of a gate insulating film is, e.g., 1.0X10 V/cm at a normal temperature. Thus the latch up of the parasitic thyristor can be prevented.

6. 发明专利

JPS61123184A Conduction modulation type mosfet 失效
标题翻译：导体调制型MOSFET
公开(公告)号：JPS61123184A
公开(公告)日：1986-06-11
申请号：JP24481184
申请日：1984-11-20
申请人： Toshiba Corp
发明人： NAKAGAWA AKIO , OHASHI HIROMICHI , YAMAGUCHI YOSHIHIRO , WATANABE KIMINORI
IPC分类号： H01L29/78 , H01L29/08 , H01L29/739
摘要： PURPOSE: To obtain a conduction modulation type MOSFET capable of being used in the same manner as a normal power MOSFET and a bipolar Tr by setting a paprmeter value so as to satisfy predetermined relationship in order to make a current value on a latch-up larger than that on the saturation of a channel region.
CONSTITUTION: An n
+ type layer 12 and a high-resistance n
- type layer 13 are formed onto a p
+ type Si sbstrate, and a p
+ type guard ring layer 22 is shaped outside an effective element region while a p
+ type layer 16 is formed. Gate electrodes 19 are shaped through gate oxide films 18, and a diffusion layer 14 is formed while using the gate electrodes 19 as masks. A p
+ type layer 15 is shaped into the layer 14, As is implanted to form n
+ type source diffusion layers 17, and channel regions 21 are shaped. A source electrode 20 and a drain electrode 23 are formed. When the whole channel width per the unit area of the region 21 is represented by W, the area of the gate electrode 19 by Sa, the whole outer-circumferential length of the base diffusion layer 14 in the unit area by T, and the thickness of the gate insulating film 18 by (d), a para sitic thyristor is not latched up by satisfying a formula: (W.Sa)/(T.l.d) 8 .
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：为了获得能够以与正常功率MOSFET和双极型Tr相同的方式使用传导调制型MOSFET，通过将树脂计数器值设定为满足预定关系，以使闩锁电流值变大比在通道区域的饱和度。构成：在ap +型Si基板上形成n +型层12和高电阻n +型层13，将ap +型保护环22形成在有效元件区域的外侧而形成ap +型层16。栅电极19通过栅极氧化膜18成形，并且在使用栅电极19作为掩模的同时形成扩散层14。将p +型层15成形为层14，As被注入以形成n +型源极扩散层17，并且沟道区21成形。形成源电极20和漏电极23。当区域21的单位面积的整个通道宽度由W表示时，栅电极19的面积为Sa，基底扩散层14的单位面积的整个外周长度为T，厚度通过（d）的栅极绝缘膜18，不能通过满足公式（W.Sa）/（Tld）<1.1×10 8来闭锁对位晶闸管。

7. 发明专利

JPH10173184A LATERAL CONDUCTION MODULATING MODE MOSFET 失效
公开(公告)号：JPH10173184A
公开(公告)日：1998-06-26
申请号：JP24272997
申请日：1997-09-08
申请人： TOSHIBA CORP
发明人： NAKAGAWA AKIO , YAMAGUCHI YOSHIHIRO , WATANABE KIMINORI , OHASHI HIROMICHI
IPC分类号： H01L29/78 , H01L29/739
摘要： PROBLEM TO BE SOLVED: To reduce the resistance of the base layer present below the channel region of a MOSFET and prevent its latchup, by so disposing an exposed portion of its high-resistance layer to its wafer surface as to have island-form patterns enclosed completely by the base layer. SOLUTION: Forming an n -type high-resistance layer 32 on a P -type layer 31, a P-type base diffusion layer 33 is formed selectively in the surface portion of the n -type high-resistance layer 32. Hereupon, the diffusion patterns of the P-type base diffusion layer 33 and the n -type high-resistance layer 32 are so formed that an exposed portion of the n -type high-resistance layer 32 to the wafer surface of a MOSFET has island-form patterns enclosed completely by the P-type base fiffusion layer 33. Then, n -type source diffusion layers 34 are formed selectively in the surface portion of the base diffusion layer 33, and a gate electrode 36 is disposed via a gate insulation layer 35 on the P-type diffusion layer portion 33 to be a channel region 38. Further, a source electrode 37 is disposed over both the n -type source diffusion layers 34 and the P-type base diffusion layer 33, and a P -type drain layer 40 is formed above the high-resistance layer 32.

8. 发明专利

JPH05235332A 失效
公开(公告)号：JPH05235332A
公开(公告)日：1993-09-10
申请号：JP13909292
申请日：1992-05-29
申请人： TOSHIBA CORP
发明人： OGURA TSUNEO , WATANABE KIMINORI , NAKAGAWA AKIO , YAMAGUCHI YOSHIHIRO , YASUHARA NORIO , SUESHIRO TOMOKO
IPC分类号： H01L29/74 , H01L29/749
摘要： PURPOSE:To provide a thyristor with an insulated gate, the turn-OFF performance of which is improved. CONSTITUTION:In thyristor structure composed of a p-type emitter layer 4, an n-type base layer 1, a p-type base layer 2 and an n-type emitter layer 3, a drain electrode 8 brought into contact with the p-type base layer 2 is formed at a position adjacent to one side of the n-type emitter layer 3, and an n-type drain electrode 7 short-circuited with the p-type base layer 2 by the drain electrode 8 is shaped. An n-type source layer 11 is formed separated at a fixed distance from the n-type drain layer 7, and an insulated gate electrode 10 for turn-off is formed between these n-type source layer 11 and n-type drain layer 7. A source electrode 12 is connected to a cathode electrode 5.

9. 发明专利

JPH02224274A CONDUCTIVITY MODULATION TYPE MOS FET 失效
公开(公告)号：JPH02224274A
公开(公告)日：1990-09-06
申请号：JP12360189
申请日：1989-05-17
申请人： TOSHIBA CORP
发明人： YAMAGUCHI YOSHIHIRO , WATANABE KIMINORI , NAKAGAWA AKIO
IPC分类号： H01L29/68 , H01L29/76 , H01L29/78
摘要： PURPOSE:To realize an anode short-circuit structure and hence keep on-voltage at a low level without causing an increased device area and reduced withstand voltage by providing an n-type cathode layer kept at the same potential as that of a drain layer independent of an n-type base layer. CONSTITUTION:A second conductivity type cathode layer 13, that adjoins to a second conductivity type base layer 3 including a first conductivity type drain layer 8 formed thereon, and that is isolated from the second conductivity type base layer 3 via a pn junction, is provided, with which cathode layer 13 a cathode electrode, that is set at the same potential as that of a drain electrode 11, that is set at the same potential as that of a drain electrode 11, is allowed to make contact. Hereby, a substantially anode short-circuit structure is realized in its high injection state. Further, since the n-type base layer 3 and the n-type cathode layer 13 are separated from each other via a pn junction, low ionic potential characteristic is assured without causing an increased device area and lowered withstand voltage.

10. 发明专利

JPH0225052A MANUFACTURE OF DIELECTRIC-ISOLATED SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0225052A
公开(公告)日：1990-01-26
申请号：JP17442888
申请日：1988-07-13
申请人： TOSHIBA CORP , TOSHIBA F A SYSTEM ENG
发明人： YAMAGUCHI YOSHIHIRO , WATANABE KIMINORI , TANZAWA KATSUJIRO , AKIHIRO HARUNOBU
IPC分类号： H01L21/762 , H01L21/76 , H01L27/08 , H01L29/41 , H01L29/78 , H01L29/866
摘要： PURPOSE:To protect wires running across an element isolating region from step-caused disconnections and to enhance device reliability by a method wherein ions are implanted through an insulating film first formed on an isolating region in a dielectric-isolated substrate. CONSTITUTION:On the entire surface of a dielectric-isolated substrate, a silicon oxide film 9 is formed, after which a silicon nitride film 10 is formed. The silicon oxide film 9 is approximately 0.1mums thick, serving as a stopper in the selective etching of the silicon nitride film 10. Next, a photoresist pattern is formed to cover the silicon nitride film 10, and the photoresist pattern serves as a mask in a boron ion implantation process accomplished, with the silicon oxide film 9 retained, for the formation of a p -type layer 11. Next, the entire substrate is subjected to thermal oxidation, which thickens the silicon oxide film 9 where it is not covered by the silicon nitride film 10. A process followed wherein the silicon nitride film 10 is removed, ions are implanted through the silicon oxide film 9, which process results in an n -type layer 12 in an island- shape Si layer 6. Using this method, unnecessary grooves are not produced in an element-isolating region, wires are protected from step-caused disconnections, and devices are improved in reliability.

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