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    • 1. 发明专利
    • SOLID-STATE IMAGE PICKUP UNIT
    • JPH09163243A
    • 1997-06-20
    • JP32169995
    • 1995-12-11
    • TOSHIBA CORP
    • KOMATSU TETSUOANDO TETSUOATSUMI KOICHIRO
    • H01L27/14H04N5/335H04N5/372
    • PROBLEM TO BE SOLVED: To miniaturize the whole unit without deteriorating an optical characteristic by providing a light transmitting part keeping airtight on the solid-state image pickup element side of a case and a means keeping airtight on the light receiving surface of a solid-state image pickup element which is arranged at the opposite side to the light receiving surface of the solid-state image pickup element. SOLUTION: The periphery of a filter constituting the light transmitting part 40 or the periphery of optical glass 43 is sealed by an adhesive B to the inner wall surface of the case 21. A substrate 50 is arranged in the lower part of the filter 43 and its periphery is sealed by the adhesive B on the inner wall surface of the case 21. A square-shaped CCD (solid-state image pickup element) chip 60 is arranged on the substrate 50. The CCD chip 60 is airtightly sealed by the filter 43 and the substrate 50 which are sealed by the adhesive B and the inner wall surface of the case 21. An external edge part as the sealing margin of the substrate 50 is not required so that the diameter of the substrate 50 is made small.
    • 7. 发明专利
    • SEMICONDUCTOR DEVICE
    • JPH04144142A
    • 1992-05-18
    • JP26747190
    • 1990-10-04
    • TOSHIBA CORP
    • ATSUMI KOICHIRO
    • H01L21/60
    • PURPOSE:To ensure multi-pin connection at the low cost by molding with protective resin a circuit pattern connection part of a lead frame, a semiconductor chip, and a circuit pattern, and protruding one end of the lead frame. CONSTITUTION:There are provided two types of lead wires 4a..., 4b... where an inner lead part is protruded inwardly from the peripheral edges of device holes 2a, 2b. The one lead wires 4a... include test pads 5 at the other end as an outer lead. The other lead wires 4b... are provided over their device holes 2a, 2b. In the device holes 2a, 2b first and second semiconductor chips 6a and 6b each having optimum areas are fitted. Further, a bump and an inner lead part on electrode (not shown here) are integrally joined and connected with each other. Since there is provided a film carrier tape F using such a TAB technique as above, a multi-chip type where the semiconductor chips 6a, 6b, can be constructed in which the semiconductor chips 6a, 6b are connected to one circuit pattern 3.
    • 9. 发明专利
    • SEMICONDUCTOR DEVICE
    • JPH03123042A
    • 1991-05-24
    • JP25876389
    • 1989-10-05
    • TOSHIBA CORP
    • ATSUMI KOICHIROMAEHARA YOICHIRO
    • H01L21/60H01L23/50
    • PURPOSE:To eliminate the need to be nervous about a difference between thermal expansion coefficients at the time of resin mold, to adhere inner lead parts diretly en block to electrode pads, to provide the electrode pads at fine pitches and to make possible the reliable connection between a lead frame and a semiconductor chip by a method wherein the wall thickness only of the inner lead parts of the lead frame is made very thinner than the wall thickness of the outer lead parts of the lead frame and the wall thickness of the parts, which are located in the vicinities of the iiner lead parts, of the outer lead parts. CONSTITUTION:Electrode pads 12 which are a multitude of connecting terminals are provided on the four sides of a semiconductor chip 11 at very fine pitches, each pad 12 is provided with a metal bump 13 and the pitches between the bumps 13 is set at a very fine pitch. On the other hand, the wall thickness M1 only of inner lead parts 14a, which are connecting parts of a lead frame 14 to the chip 11, is formed in a very thin wall thickness and the wall thickness of outer lead parts 14b other than these lead parts 14a and the wall thickness of the parts, which are located in the vicinities of the lead parts 14a, of the lead parts 14b are formed in a normal wall thickness M0. The bumps 13 are pressed by a heating tool through the lead parts 14a of the lead frame 14 and the pads 12 and the lead parts 14a are bonded together en block.
    • 10. 发明专利
    • MANUFACTURE OF SEMICONDUCTOR DEVICE
    • JPH03120842A
    • 1991-05-23
    • JP25778789
    • 1989-10-04
    • TOSHIBA CORP
    • KASHIMA NORIYASUATSUMI KOICHIROIKETANI YUKIHIRO
    • H01L21/50
    • PURPOSE:To obtain a device which is excellent in workability and able to reduce the generation of defects, by linking an inner lead bonding equipment and a potting equipment, and making a carrier tape continuously run from the inner lead bonding equipment to the potting equipment. CONSTITUTION:In a manufacturing equipment 21 of a semiconductor device wherein a film carrier 3 for mounting semiconductor elements is made to run, at least an inner lead bonding equipment 1 mounting a semiconductor element 7 on the film carrier 3 and a potting equipment 11 coating the semiconductor element 7 mounted on the film carrier 3 with sealing resin are linked, and a carrier tape is made to continuously run from the inner lead bonding equipment 1 to the potting equipment 11. Further, for example, after the semiconductor element 7 coated with resin is conveyed in a curing furnace 15 as it remains horizontal for a while, and the resin is cured until it turns to a gel state, the element is brought into contact with a guide roller 16, and the resin is further cured while the film carrier 3 is intermittently sent.