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1. 发明专利

JP2007066364A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007066364A
公开(公告)日：2007-03-15
申请号：JP2005248838
申请日：2005-08-30
申请人： Sony Corp , ソニー株式会社
发明人： YAMAMURA YASUHIRO
IPC分类号： G11C11/36 , H01L21/8229 , H01L21/8244 , H01L27/102 , H01L27/11
摘要： PROBLEM TO BE SOLVED: To reduce the size of a memory cell in a semiconductor device having the memory cells made of access transistors and thyristors.
SOLUTION: This semiconductor device has memory cells having access transistors 11 and negative resistor elements (thyristors) 12, 13 connected in parallel to the access transistors 11. The thyristors have gate electrodes 12G, 13G to control turn-on and turn-off.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了减小具有由存取晶体管和晶闸管构成的存储单元的半导体器件中的存储单元的尺寸。解决方案：该半导体器件具有存储单元，存储单元具有与存取晶体管11并联连接的存取晶体管11和负电阻元件（晶闸管）12,13。晶闸管具有栅电极12G，13G以控制导通和转向，关闭。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2010086638A Variable resistance memory device, and operating method of the same 审中-公开
标题翻译：可变电阻存储器件及其操作方法
公开(公告)号：JP2010086638A
公开(公告)日：2010-04-15
申请号：JP2008257714
申请日：2008-10-02
申请人： Sony Corp , ソニー株式会社
发明人： MIYATA KOJI , YAMAMURA YASUHIRO , MORI HIRONOBU
IPC分类号： G11C11/15 , G11C13/00
CPC分类号： G11C11/1659 , G11C11/1673
摘要： PROBLEM TO BE SOLVED: To cancel variations in circuit elements on the basis of the results of detecting the resistance changes. SOLUTION: The variable resistance memory device has a memory cell MC including a tunneling magnetoresistive element TMR and a drive circuit 5A. The drive circuit 5A includes a first and second resistors R1, R2 different from each other and generates a drive voltage Vbias to be applied to the power supply node Nd by supplying a constant current Ic through the first resistor R1 or the second resistor R2. The drive circuit 5A differentially switches the resistor generating the drive voltage Vbias and the pull-up resistor compensating the power supply node Nd potential falling depending on the cell current, by using the first and second resistors R1, R2. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：基于检测电阻变化的结果来消除电路元件的变化。解决方案：可变电阻存储器件具有包括隧道磁阻元件TMR和驱动电路5A的存储单元MC。驱动电路5A包括彼此不同的第一和第二电阻器R1，R2，并且通过经由第一电阻器R1或第二电阻器R2提供恒定电流Ic来产生施加到电源节点Nd的驱动电压Vbias。通过使用第一和第二电阻R1，R2，驱动电路5A差分地切换产生驱动电压Vbias的电阻和上拉电阻，该上拉电阻补偿根据电池电流而下降的电源节点Nd电位。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2003332420A Method for manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2003332420A
公开(公告)日：2003-11-21
申请号：JP2002135946
申请日：2002-05-10
申请人： Sony Corp , ソニー株式会社
发明人： YAMAMURA YASUHIRO
IPC分类号： H01L21/3065 , H01L21/768 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device wherein irregularity of depth of a wiring trench and a connection hole is restrained, the wiring trench and the connection hole can be formed without damaging a lower layer wiring, and a stable dual damascene structure can be formed. SOLUTION: An insulating film 15 for forming the connection hole, a stopper layer 16 of etching, an insulating film 17 for forming the wiring trench, and a mask layer 18 are formed on the lower layer wiring W1. Elimination by etching is performed as far as a middle point of the insulating film 15, and an aperture C turning to a pattern of the connection hole is formed. An aperture is formed on the mask layer 18 so as to become a pattern of the wiring trench, and the insulating film 17 and the insulating film 15 are eliminated by etching using the mask layer 18 as a mask, until the stopper layer 16 is exposed. The wiring trench is formed on the insulating film 17, and the connection hole reaching the lower layer wiring is formed on the insulating film 15. COPYRIGHT: (C)2004,JPO
摘要翻译：解决的问题：为了提供一种制造半导体器件的方法，其中布线沟槽和连接孔的深度不均匀被限制，可以形成布线沟槽和连接孔而不损坏下层布线，并且可以形成稳定的双镶嵌结构。解决方案：在下层布线W1上形成用于形成连接孔的绝缘膜15，蚀刻用阻挡层16，用于形成布线沟槽的绝缘膜17和掩模层18。通过蚀刻进行绝缘膜15的中间点的形成，形成连接孔图案的孔C。在掩模层18上形成开口以成为布线沟槽的图案，并且通过使用掩模层18作为掩模的蚀刻来消除绝缘膜17和绝缘膜15，直到阻挡层16暴露。布线沟槽形成在绝缘膜17上，并且到达下层布线的连接孔形成在绝缘膜15上。版权所有（C）2004，JPO

4. 发明专利

JP2003324189A Solid-state image pickup element and solid-state image pickup device and method for manufacturing the same 有权
标题翻译：固态图像拾取元件和固态图像拾取器件及其制造方法
公开(公告)号：JP2003324189A
公开(公告)日：2003-11-14
申请号：JP2002129780
申请日：2002-05-01
申请人： Sony Corp , ソニー株式会社
发明人： YAMAMURA YASUHIRO
IPC分类号： H01L27/14 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L27/146 , H01L29/04 , H04N5/335 , H04N5/369 , H04N5/372 , H04N5/374
CPC分类号： H01L27/14636 , H01L27/1462 , H01L27/14623 , Y10S438/927
摘要： PROBLEM TO BE SOLVED: To provide a solid-state image pickup element and a solid-state image pickup device for satisfactorily making light incident to a light receiving part even if using a material having the different refractivity of the transmitted light for preventing the diffusion of wiring materials, and to provide a method for manufacturing the solid-state image pickup element and device.
SOLUTION: Diffusion preventing films 5a, 5b and 5c of wiring materials are disposed in a region other than a light receiving part 2 with a plane view by selectively removing the diffusion preventing films 5a, 5b, and 5c formed in the upper region of the light receiving part 2, or disposing the diffusion preventing films only on upper faces of wiring 4a, 4b, and 4c. Then, only a passivation film 12 and inter-layer insulating films 3a, 3b, and 3c are disposed in the upper region of the light receiving part 2. Thus, it is possible to reduce the interface of different kinds of insulating films in a light incident region, and to reduce the reflection of the incident light. Furthermore, the light 13 is made incident through those insulating films to the light receiving part 2 with high efficiency so that the incident light 13 can be received by the light receiving part 2 with a sufficient light quantity.
COPYRIGHT: (C)2004,JPO
摘要翻译：解决的问题：为了提供固态摄像元件和固态摄像装置，即使使用具有不同的透射光的折射率的材料来防止光入射到光接收部分，布线材料的扩散，并且提供一种用于制造固态图像拾取元件和装置的方法。解决方案：通过选择性地除去形成在上部区域中的扩散防止膜5a，5b和5c，布线材料的防扩散膜5a，5b和5c通过平面视图设置在除了光接收部分2之外的区域中或者仅将扩散防止膜设置在布线4a，4b，4c的上表面上。然后，只有钝化膜12和层间绝缘膜3a，3b和3c设置在光接收部分2的上部区域中。因此，可以减少光的不同种类的绝缘膜的界面入射区域，并减少入射光的反射。此外，光13通过这些绝缘膜以高效率入射到光接收部分2，使得入射光13能够被光接收部分2以足够的光量被接收。版权所有（C）2004，JPO

5. 发明专利

JP2011216672A Solid-state image pickup device, method for manufacturing solid-state image pickup device, and electronic apparatus 有权
标题翻译：固态图像拾取装置，制造固态图像拾取装置的方法和电子装置
公开(公告)号：JP2011216672A
公开(公告)日：2011-10-27
申请号：JP2010083597
申请日：2010-03-31
申请人： Sony Corp , ソニー株式会社
发明人： OIKE YUSUKE , KAWAMURA TAKAHIRO , YAMAKAWA MASAYA , YAMAMURA YASUHIRO , MACHIDA TAKASHI , SOGO YASUNORI , SAKA NAOKI
IPC分类号： H01L27/146 , H04N5/359 , H04N5/374 , H04N5/3745 , H04N101/00
CPC分类号： H01L27/14612 , H01L27/14601 , H01L27/14616 , H01L27/14643 , H01L27/14656 , H01L27/14689 , H01L27/14806 , H01L27/14862 , H04N5/353 , H04N5/363 , H04N5/37452
摘要： PROBLEM TO BE SOLVED: To allow obtaining an image of high picture quality.SOLUTION: A unit pixel 120C is equipped with: a photodiode 121 which generates an electric charge corresponding to the incident light amount for accumulating the charge inside the photodiode; a memory part 123 which holds the electric charge having been converted by the photodiode 121 until it is read out; and a first transfer gate 122 which contains a complete transfer path 150 which transfers all electric charges accumulated in the photodiode 121 to the memory part 123, and an intermediate transfer path 140 that transfers only the electric charge that exceeds a predetermined amount of electric charge that has occurred at the photodiode 121 to the memory part 123 during exposure period. The complete transfer path 150 and the intermediate transfer path 140 are formed in different regions, The invention can apply to a solid-state image pickup device, for example.
摘要翻译：要解决的问题：允许获得高图像质量的图像。解决方案：单元像素120C配备有：光电二极管121，其产生对应于入射光量的电荷，用于在光电二极管内累积电荷; 存储部123，其保持由光电二极管121转换的电荷，直到读出; 以及第一传送门122，其包含将累积在光电二极管121中的所有电荷传送到存储器部123的完整传送路径150以及仅传送超过预定电荷量的电荷的中间传送路径140，在曝光期间在光电二极管121发生到存储部123。完整的传送路径150和中间传送路径140形成在不同的区域中。例如，本发明可以应用于固态图像拾取装置。

6. 发明专利

JP2007067133A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2007067133A
公开(公告)日：2007-03-15
申请号：JP2005250615
申请日：2005-08-31
申请人： Sony Corp , ソニー株式会社
发明人： YAMAMURA YASUHIRO
IPC分类号： H01L21/8229 , H01L21/8244 , H01L27/102 , H01L27/11
CPC分类号： H01L27/1027 , H01L27/11
摘要： PROBLEM TO BE SOLVED: To prevent the occurrence of a vertical parasitic thyristor and reduce the memory cell size by using a cheap bulk semiconductor substrate. SOLUTION: The semiconductor device 1 includes an access transistor 40 formed on the bulk semiconductor substrate 11, a thyristor 20, and an element isolation region 13 for isolating both of them. A wiring layer 51 is provided to connect one source, drain region 45 of the access transistor 40 and the N-type impurity layer 24 on the cathode side of the thyristor 20 together through a connection hole 52. In the structure of the impurity region on the anode side of the thyristor 20, a P-type impurity layer 21, an N-type impurity layer 22, a P-type well 14 (p-type impurity layer 23), and an N-type well 12 are formed in this order in the depthwise direction, and the same voltage as applied to the anode upon data holding is applied to the lowermost N-type well 12. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了防止垂直寄生晶闸管的发生，并且通过使用便宜的体积半导体衬底来减小存储单元尺寸。解决方案：半导体器件1包括形成在体半导体衬底11上的存取晶体管40，晶闸管20和用于隔离它们的元件隔离区13。布线层51设置成通过连接孔52将存取晶体管40的一个源极，漏极区域45和晶闸管20的阴极侧上的N型杂质层24连接在一起。在杂质区域的结构在这种情况下形成晶闸管20的阳极侧，P型杂质层21，N型杂质层22，P型阱14（p型杂质层23）和N型阱12 在深度方向上排列，并且将数据保持时施加到阳极上的相同电压施加到最下面的N型阱12.版权所有：（C）2007，JPO＆INPIT

7. 发明专利

JP2004071790A Solid state imaging device and its manufacturing method 有权
公开(公告)号：JP2004071790A
公开(公告)日：2004-03-04
申请号：JP2002228402
申请日：2002-08-06
申请人： Sony Corp , ソニー株式会社
发明人： YAMAMURA YASUHIRO
IPC分类号： H01L27/146 , H01L27/14 , H04N5/335 , H04N5/369 , H04N5/374
摘要： PROBLEM TO BE SOLVED: To restrain deterioration of light receiving efficiency and sensitivity of an imaging device which is caused by a dummy wiring, in a constitution wherein the imaging device in which a plurality of light receiving parts are arranged and a peripheral circuit of the imaging device are arranged on the same semiconductor substrate.
SOLUTION: Wirings 120, 122, 124 of lower three layers out of wirings of the imaging device 129 and the peripheral circuit 130 are common to the peripheral circuit 130 and the imaging device 129. A wiring 126 of the uppermost layer is formed only in the peripheral circuit 130 and not formed in the imaging device 129. That is, the wiring 126 of the uppermost layer is formed as the dummy wiring 126A in the imaging device 129 side. Since the dummy wiring 126A causes deterioration of light receiving efficiency to each photoelectric conversion 118 of the imaging device 129, the dummy wiring 126A is eliminated from the imaging device 129, so that improvement of light receiving efficiency and sensitivity is realized.
COPYRIGHT: (C)2004,JPO

8. 发明专利

JP2003332421A Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2003332421A
公开(公告)日：2003-11-21
申请号：JP2002136080
申请日：2002-05-10
申请人： Sony Corp , ソニー株式会社
发明人： YAMAMURA YASUHIRO
IPC分类号： H01L21/28 , H01L21/3065 , H01L21/768
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device wherein embedding property of a conducting material into a connection hole can be improved, in the state that a connection area with lower layer wiring is ensured while irregularity of depth of a wiring trench and the connection hole is restrained.
SOLUTION: A first insulating film 15 is formed on the lower layer wiring W1, a stopper layer 16 of etching is formed on the first insulating film 15, a second insulating film 17 is formed on the stopper layer 16, the second insulating film 17, the stopper layer 16 and the first insulating film 15 are eliminated by etching, and a connection hole 15a is formed. The second insulating film 17 is eliminated by etching until the stopper layer 16 is exposed, and the wiring trench 17a is formed on the second insulating film 17. Etching is continued further, the stopper layer 16 in a linkage part of the wiring trench 17a and the connection hole 15a and the first insulating film 15 are ground, a diameter of an end portion of the connection hole 15a on a wiring trench 17a side is enlarged, and the wiring trench 17a and the connection hole 15a are filled with the conducting material.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种制造半导体器件的方法，其中可以提高导电材料在连接孔中的嵌入性能，同时确保与下层布线的连接区域，同时深度不均匀的状态布线沟槽和连接孔被限制。解决方案：在下层布线W1上形成第一绝缘膜15，在第一绝缘膜15上形成蚀刻停止层16，在阻挡层16上形成第二绝缘膜17，第二绝缘膜通过蚀刻除去膜17，阻挡层16和第一绝缘膜15，形成连接孔15a。通过蚀刻去除第二绝缘膜17，直到停止层16露出，并且布线沟槽17a形成在第二绝缘膜17上。进一步蚀刻，布线沟槽17a的连接部分中的阻挡层16和连接孔15a和第一绝缘膜15被研磨，布线沟槽17a侧的连接孔15a的端部的直径扩大，并且布线沟槽17a和连接孔15a填充有导电材料。版权所有（C）2004，JPO

9. 发明专利

JP2007200520A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2007200520A
公开(公告)日：2007-08-09
申请号：JP2006322660
申请日：2006-11-29
申请人： Sony Corp , ソニー株式会社
发明人： YAMAMURA YASUHIRO
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/11
CPC分类号： G11C11/412 , G11C5/145
摘要： PROBLEM TO BE SOLVED: To achieve simultaneously a stable write operation during writing and an accelerated reading operation or prevention of malfunction when a part of a memory cell connected to the same word line is written.
SOLUTION: The device has a pair of inverters (P1 and N1, P2 and N2), a feed control switch P3 connected between the feeding point NDdd of the pair of inverters and a power supply voltage supply line 4, and a boosting device (capacitor 5) configured to boost voltage of the feeding point NDdd electrically isolated from the power supply voltage supply line 4 by the feed control switch P3, for each SRAM cell 1A.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：当写入连接到同一字线的存储单元的一部分被写入时，在写入期间和加速读取操作期间同时实现稳定的写入操作或防止故障。
解决方案：该装置具有一对反相器（P1和N1，P2和N2），连接在一对反相器的馈电点NDdd与电源电压供应线4之间的馈电控制开关P3和升压被配置为通过馈电控制开关P3对每个SRAM单元1A升压与电源电压供应线路4电隔离的馈电点NDdd的电压的装置（电容器5）。版权所有（C）2007，JPO＆INPIT

10. 发明专利

JP2007053127A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007053127A
公开(公告)日：2007-03-01
申请号：JP2005235162
申请日：2005-08-15
申请人： Sony Corp , ソニー株式会社
发明人： NAKAMURA MOTOAKI , YAMAMURA YASUHIRO
IPC分类号： H01L29/749 , H01L21/8234 , H01L27/06 , H01L27/088
摘要： PROBLEM TO BE SOLVED: To reduce an element area without remarkably changing a conventional CMOS thyristor process by forming one part of a thyristor on a semiconductor substrate.
SOLUTION: The semiconductor device 1 is formed on a semiconductor substrate 11 and provided with the tyristor 20 equipped with a MIS type gate 30. The thyristor 20 is configured in such a way that a first conductive first region 21, a second conductive second region 22 of a conductive type opposite to the first conductive region 21, a first conductive type third region 23, and a second conductive type fourth region 24 are connected in series. The first, second and third regions 21, 22 and 23 are formed on the semiconductor substrate 11, the third region 23 is formed so as to be erected upward from the surface of the semiconductor substrate 11, and the fourth region 24 is formed on the third region 23 formed so as to be erected upward.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：通过在半导体衬底上形成晶闸管的一部分来减少元件面积而不会显着地改变传统的CMOS晶闸管工艺。解决方案：半导体器件1形成在半导体衬底11上，并配备有配有MIS型栅极30的可控硅20.晶闸管20被配置成使得第一导电第一区21，第二导电与第一导电区域21相反的导电类型的第二区域22，第一导电类型第三区域23和第二导电类型第四区域24串联连接。第一，第二和第三区域21,22和23形成在半导体衬底11上，第三区域23形成为从半导体衬底11的表面向上竖立，并且第四区域24形成在第三区域23形成为向上竖起。版权所有（C）2007，JPO＆INPIT

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