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1. 发明专利

JP2010002222A Delay measuring device and semiconductor device 审中-公开
标题翻译：延迟测量装置和半导体器件
公开(公告)号：JP2010002222A
公开(公告)日：2010-01-07
申请号：JP2008159470
申请日：2008-06-18
申请人： Sony Corp , ソニー株式会社
发明人： MEGURO TETSUMASA
IPC分类号： G01R31/28 , H01L21/82 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To evaluate an instantaneous delay, and to obtain high detection accuracy.
SOLUTION: A delay measuring device includes; a pulse generating circuit 11 for generating a reference pulse PS1 and a measuring pulse PS2 at respective prescribed timing; and a delay measuring circuit 12. The delay measuring circuit 12 inputs the reference pulse PS1 from the pulse generating circuit 11 and inputs a delayed pulse PS2d from a circuit to be measured 20 which is obtained after a propagation delay in an operation of inputting the measuring pulse PS2 to the circuit to be measured 20. The delay measuring circuit 12 detects a phase difference between the reference pulse PS1 and the delayed pulse PS2d at the start or end timing of the pulses, and outputs delay information representing the detected phase difference.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：评估瞬时延迟并获得高检测精度。解决方案：延迟测量装置包括：脉冲发生电路11，用于在各自规定的时刻产生参考脉冲PS1和测量脉冲PS2; 和延迟测量电路12.延迟测量电路12从脉冲发生电路11输入参考脉冲PS1，并从输入测量的操作中的传播延迟之后获得的待测电路20的延迟脉冲PS2d输入脉冲PS2到要测量的电路20.延迟测量电路12在脉冲的开始或结束定时检测参考脉冲PS1和延迟脉冲PS2d之间的相位差，并输出表示检测到的相位差的延迟信息。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2005322860A Semiconductor integrated circuit and method for testing same 有权
标题翻译：半导体集成电路及其测试方法
公开(公告)号：JP2005322860A
公开(公告)日：2005-11-17
申请号：JP2004141614
申请日：2004-05-11
申请人： Sony Corp , ソニー株式会社
发明人： MEGURO TETSUMASA , KUROSE ETSUKAZU
IPC分类号： G01R31/28 , G11C7/00 , G11C29/02 , H01L21/66 , H01L21/82 , H01L21/822 , H01L27/04
CPC分类号： G11C29/021 , G11C29/02 , G11C29/028 , G11C2029/0403 , G11C2029/4402 , G11C2029/5004
摘要： PROBLEM TO BE SOLVED: To provide semiconductor integrated circuits which can be driven by respectively different power supply voltages in accordance with manufacturing dispersion, and provide a test method for guaranteeing the operation.
SOLUTION: In addition to a function block to be driven by receiving supply of power supply voltage, the semiconductor integrated circuit 10 comprises a process monitor circuit 11 for grasping a delay characteristic corresponding to a manufacturing process condition; a storage circuit 12 for storing data concerned with a process dispersion state acquired from the process monitor circuit 11; and a power supply voltage control circuit 13 for adaptively controlling the power supply voltage in accordance with the process dispersion state acquired from the process monitor circuit 11 and stored in the storage circuit 12.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供根据制造分散可分别由不同电源电压驱动的半导体集成电路，并提供用于保证操作的测试方法。解决方案：半导体集成电路10除了通过接收电源电压的驱动而驱动的功能块之外，还包括用于掌握对应于制造工艺条件的延迟特性的处理监视电路11。用于存储与从处理监视电路11获取的处理色散状态有关的数据的存储电路12; 以及电源电压控制电路13，用于根据从处理监视电路11获取并存储在存储电路12中的处理色散状态自适应地控制电源电压。（C）2006年，JPO＆NCIPI

3. 发明专利

JP2004032875A Electronic equipment 有权
公开(公告)号：JP2004032875A
公开(公告)日：2004-01-29
申请号：JP2002184103
申请日：2002-06-25
申请人： Sony Corp , ソニー株式会社
发明人： SEKI TAKEHIRO , NAKAI MASAKATSU , MEGURO TETSUMASA
IPC分类号： H02M3/155
摘要： PROBLEM TO BE SOLVED: To provide an electronic equipment which can suppress the overhead caused by the switchover of a control system and can keep a switching regulator in high efficiency within a wide load current range.
SOLUTION: This electronic equipment is provided with a load circuit 44 which outputs a rectification system switching signal S45 to instruct a switching regulator 41 to operate in PWW control and synchronous rectification system in active mode, and outputs a rectification system switching signal S45 to instruct the switching regulator 41 to operate in diode rectification system in standby mode; and the above-mentioned switching regulator 41 which includes a control circuit 419 for judging whether to drive it in synchronous rectification system or to drive it in diode rectification system according to the instruction of the rectification system switching signal S45, outputting control signals CTL1 and CTL2 to driver circuits 420 and 421 according to the judged rectification system, and performing the drive control of a p-channel switching transistor 411 and an n-channel switching transistor 412.
COPYRIGHT: (C)2004,JPO

4. 发明专利

JP2003330569A Clock generator and clock conversion circuit 有权
标题翻译：时钟发生器和时钟转换电路
公开(公告)号：JP2003330569A
公开(公告)日：2003-11-21
申请号：JP2002138020
申请日：2002-05-14
申请人： Sony Corp , ソニー株式会社
发明人： MEGURO TETSUMASA
IPC分类号： G06F1/04 , G06F1/06 , G06F1/08 , G06F1/32 , H03K5/00 , H03K23/64
CPC分类号： G06F1/08 , G06F1/3203 , Y02D10/126
摘要： PROBLEM TO BE SOLVED: To solve a problem that a frequency not suitable for a task is often generated with a clock generator which generates clocks of a plurality of frequencies, and that useless power is consumed in that event. SOLUTION: The clock generator includes: a clock generater 11 which generates clocks clk of predetermined frequencies; a counter 13 which operates in synchronization with the clock clk and counts pulses of the clock clk; a comparator 14 which compares the counter value of the counter 13 with the number of pulses cmpd of the clock of a desired frequency freq; and output gates 15, 16 which control the supply and half of the pulse of the clock clk inputted from the clock generation part 11, on the basis of the comparison result obtained with the comparator 14. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：为了解决通常使用产生多个频率的时钟的时钟发生器来生成不适合任务的频率的问题，并且在该事件中消耗无用功率的问题。时钟发生器包括：时钟发生器11，其生成预定频率的时钟clk; 计数器13，其与时钟clk同步操作并计数时钟clk的脉冲; 比较器14，其将计数器13的计数器值与期望频率的时钟的脉冲数cmpd进行比较; 以及输出门15,16，其根据比较器14获得的比较结果控制从时钟产生部分11输入的时钟clk的脉冲供应和一半的脉冲数。（C）2004， JPO

5. 发明专利

JP2004355599A Frequency control device, information processor, and program 有权
公开(公告)号：JP2004355599A
公开(公告)日：2004-12-16
申请号：JP2003272333
申请日：2003-07-09
申请人： Sony Corp , ソニー株式会社
发明人： SHIMOYAMA TAKESHI , MEGURO TETSUMASA , TERANISHI TSUTOMU , NAKANO YASURO , KAWAHARA HIROKAZU
IPC分类号： G06F1/32 , G06F1/04 , H03L7/06 , H03L7/07 , H03L7/099 , H03L7/16
CPC分类号： G06F1/324 , G06F1/3203 , H03L7/06 , H03L7/07 , H03L7/0991 , H03L7/16 , Y02D10/126
摘要： PROBLEM TO BE SOLVED: To realize improvement of performance, power saving, etc. by allowing an operation frequency to be limited or allowing an allowable value or the like to be designated in operation frequency control according with an observation result of an operating state of a control object. SOLUTION: A frequency control device 1 is provided with an observation means 3 for observing the operating state of a control object 2 operating on the basis of a variably controlled frequency, a frequency determination means for determining a clock frequency in accordance with the operating state, and a frequency limiting means 5 for limiting the range or value of the clock frequency determined by the frequency determination means 4. The control is performed in accordance with the frequency determined in accordance with the operating state of the control object 2 in the case that the frequency is within an allowable range, and the frequency is limited in the case that the frequency is on the outside of the allowable range. COPYRIGHT: (C)2005,JPO&NCIPI

6. 发明专利

JP2004179321A Semiconductor device 有权
公开(公告)号：JP2004179321A
公开(公告)日：2004-06-24
申请号：JP2002342757
申请日：2002-11-26
申请人： Sony Corp , ソニー株式会社
发明人： SEKI TAKEHIRO , NAKAI MASAKATSU , MEGURO TETSUMASA
IPC分类号： H01L27/04 , H01L21/822 , H03H11/26 , H03K5/00 , H03K5/131 , H03K5/14 , H03L7/081
CPC分类号： H03L7/0805 , H03K2005/00058 , H03L7/0814
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device with its delay monitor circuit made configurable with flexibility and with high efficiency by minimizing an increase in the circuit scale.
SOLUTION: The semiconductor device is provided with a delay signal generating circuit 142 for changing delay element line configuration based on a first configuration data CNFG1 or a second configuration data CNFG2, and for propagating the delay element line with a pulse S141 changed; a register group 145 having a first register REGa with the first configuration data CNFG1 set therein, and a second register REGb with the second configuration data CNFG2 set therein; a selector 146 for outputting the first configuration data CNFG1 and the second configuration data CNFG2 in compliance with the instruction of a selection signal S144 to the delay signal generating circuit 142 on the time-sharing basis; and a control circuit 144 for controlling the power source voltage based on the delay data on the delay element line, and for outputting the selection signal S144 to a selector 146 for selecting the first configuration data CNFG1 and the second configuration data CNFG2 on the time-sharing basis.
COPYRIGHT: (C)2004,JPO

7. 发明专利

JP2004179320A Semiconductor device 审中-公开
公开(公告)号：JP2004179320A
公开(公告)日：2004-06-24
申请号：JP2002342756
申请日：2002-11-26
申请人： Sony Corp , ソニー株式会社
发明人： MEGURO TETSUMASA , NAKAI MASAKATSU
IPC分类号： H01L21/66 , G11C11/4076 , H01L21/82 , H01L21/822 , H01L27/04 , H03K5/13
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device with its power consumption efficiently reduced by constantly setting optimum data for each LSI. SOLUTION: The semiconductor device has a replica control circuit 15 having a decoder circuit 151 for reading data to be determined by the state of fuse in the fuse circuit 152, and for generating a control signal SADJ for a replica circuit 12 by decoding the read data. The device further has a replica circuit 12 capable of selecting the number of stages in the line of elements according to the control signal SADJ indicating structural data set in the replica control circuit 15, and capable of adjusting the delay characteristics to be the same as the critical path characteristics of a target circuit 11. In this way, dispersion in characteristics due to the manufacturing process is properly dealt with after the manufacturing of LSIs. COPYRIGHT: (C)2004,JPO

8. 发明专利

JP2004054350A Clock switching circuit 审中-公开
公开(公告)号：JP2004054350A
公开(公告)日：2004-02-19
申请号：JP2002207210
申请日：2002-07-16
申请人： Sony Corp , ソニー株式会社
发明人： MEGURO TETSUMASA
IPC分类号： G06F1/04 , G06F1/06 , G06F1/08 , H03K5/13 , H03K17/62 , H04L7/00
CPC分类号： G06F1/08
摘要： PROBLEM TO BE SOLVED: To switch a first clock signal being output to a second clock signal arbitrarily selected from a plurality of clock signals having different frequencies and phases while preventing the occurrence of a hazard. SOLUTION: A clock signal clk_i (i=1, 2,..., x), a selection signal of the clock signal sel_i, and a permission signal chen are respectively input. A plurality of unit circuits 10 -1 , 10 -2 ,...10 -x controls the supply or the suspension of the clock signal corresponding to the selection signal and the permission signal. A feedback circuit 30 monitors the output states of the plurality of unit circuits, and when each of the unit circuits stops outputting the clock signal as the first clock signal stops, supplies the unit circuits with the permission signal chen for permitting the supply of the second clock signal. COPYRIGHT: (C)2004,JPO

9. 发明专利

JP2003140767A FREQUENCY CONTROL CIRCUIT 审中-公开
公开(公告)号：JP2003140767A
公开(公告)日：2003-05-16
申请号：JP2001343041
申请日：2001-11-08
申请人： SONY CORP
发明人： MEGURO TETSUMASA
IPC分类号： G06F1/32 , G06F1/04 , H03K5/00
摘要： PROBLEM TO BE SOLVED: To provide a frequency control circuit in which power consumption can be reduced without increasing the variation of a clock frequency. SOLUTION: This frequency control circuit is provided with a control circuit 15 for outputting a first control signal S151 to a clock supplying circuit 12 when a through-put T is requested in order to instruct the clock supplying circuit 12 to decide two clock frequencies and each period from the value of the through-put T and the value of a through-put to be realized from a clock frequency which can be generated by the clock supplying circuit 12, and to select those two clock frequencies in each decided period, and to output it as a system clock, and for outputting a second control signal S152 to a power supply voltage supplying circuit 13 in order to instruct the power supply voltage supplying circuit 13 to supply a power supply voltage with which the operation of a target circuit can be ensured in each of those two clock frequencies instructed to the clock supply circuit 12.

10. 发明专利

JP2003150269A POWER SUPPLY VOLTAGE FREQUENCY CONTROL CIRCUIT 审中-公开
公开(公告)号：JP2003150269A
公开(公告)日：2003-05-23
申请号：JP2001343168
申请日：2001-11-08
申请人： SONY CORP
发明人： MEGURO TETSUMASA
IPC分类号： G06F1/04 , H02M3/157 , H03K5/00
摘要： PROBLEM TO BE SOLVED: To provide a power supply voltage frequency control circuit capable of ensuring the operation of a target circuit when changing a clock frequency according to processing, and supplying a power supply voltage according to the change. SOLUTION: This circuit is provided with a clock supply circuit 12 capable of supplying a system clock SYSCLK with a plurality of clock frequency, and supplying a system clock with a clock frequency corresponding to a first control signal S141 to a target circuit 11 for performing processing synchronously with a system clock, a power supply voltage supply circuit 13 for supplying a power supply voltage whose value corresponds to a second control signal S142 to a target circuit 11, and a control circuit 14 for outputting a first control signal S141 to the clock supply circuit 12, and for outputting the second control signal S142 to the power supply voltage supply circuit 13 according to the instruction of a frequency change value and a change time from the target circuit 13.

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