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1. 发明专利

JP2000004453A VIDEO DISPLAY SWITCHING SYSTEM AND SPECTACLES FOR WATCHING VIDEO 失效
公开(公告)号：JP2000004453A
公开(公告)日：2000-01-07
申请号：JP16975898
申请日：1998-06-17
申请人： SONY CORP
发明人： KAGITA JUNJI , HARADA SHIGERU , TOKUHARA MASAHARU
IPC分类号： H04N13/04 , H04N5/64
摘要： PROBLEM TO BE SOLVED: To eliminate a trouble caused by a hard-to-watch image such as a double image in view, displaying a three-dimensional (3D) video when the wearing of spectacles is judged by a communication means and displaying a 2D video when no wearing of spectacles is judged. SOLUTION: The ON/OFF state of a switch 34 attached to spectacles 33 is supplied from the switch 34 to a monitor 31 by a cable 32. Namely, it is supplied from the ON/OFF state of the switch 34 through the cable 32 to the monitor 31 whether a viewer wears the spectacles 33 or not. According to this ON/OFF state of the switch 34, the 2D video/3D video to be displayed on the monitor 31 is switched. Therefore, only when the viewer wears the spectacles 33, the 3D video is displayed on the monitor 31 and when the viewer does not wear the spectacles 33, the 2D video can be displayed so that a hard-to- watch image can be prevented from being displayed on the monitor 31.

2. 发明专利

JPH053789B2 失效
公开(公告)号：JPH053789B2
公开(公告)日：1993-01-18
申请号：JP15292383
申请日：1983-08-22
申请人： SONY CORP
发明人： TAMURA TAKAHIKO , TOKUHARA MASAHARU
IPC分类号： H04N5/59 , H04N9/30 , H04N9/64

3. 发明专利

JPH04129413A SAMPLE RATE CONVERSION CIRCUIT 失效
公开(公告)号：JPH04129413A
公开(公告)日：1992-04-30
申请号：JP25155690
申请日：1990-09-20
申请人： SONY CORP
发明人： TOKUHARA MASAHARU , WATANABE KAZUO , TODO HIROBUMI
IPC分类号： H04N19/00 , H03H17/00 , H03H17/02 , H04N11/04 , H04N19/42 , H04N19/59 , H04N19/80 , H04N19/85
摘要： PURPOSE:To realize a sample rate conversion circuit whose circuit scale is reduced by using a multiplier in common for the processing of plural digital data. CONSTITUTION:The circuit is provided with plural 1st latch means 1a latching plural digital data at a 1st sampling clock respectively and plural 2nd latch means 2a latching again each digital data latched by each 1st latch means 1a at a 2nd sampling clock respectively. Then a digital data latched by each of the 2nd latch means 2a is outputted selectively to multipliers M0-Mn at a prescribed order with selection means SW0-SWn and the resulting data is extracted as a time division multiplex data. Since the processing of plural digital data is implemented by the multipliers M0-Mn in common and number of the multipliers M0-Mn with a highest circuit scale is reduced. Thus, the entire circuit is reduced.

4. 发明专利

JPH02210989A TELEVISION RECEIVER 失效
公开(公告)号：JPH02210989A
公开(公告)日：1990-08-22
申请号：JP26578488
申请日：1988-10-21
申请人： SONY CORP
发明人： NAITO HIDEFUMI , SARUGAKU TOSHIO , TOKUHARA MASAHARU
IPC分类号： H04N5/93 , H04N7/01
摘要： PURPOSE:To reduce flicker on the screen when a reproduced signal from a VTR is watched by shifting a vertical synchronizing pulse in the time base direction so as to appear earlier than a vertical synchronizing signal by a prescribed horizontal period. CONSTITUTION:The television receiver consists of a counter 19, latch circuits 21, 23, comparators 24, 27, a sub counter 26, an AND circuit 25 as a vertical synchronizing pulse forming means and of a sub counter 20 as a control means. A vertical synchronizing pulse forming means uses a vertical synchronizing signal VS of the standard TV signal from a terminal 18 and a clock signal from a terminal 22 to form a vertical synchronizing pulse 28a having frequency twice the frequency of the signal VS whose field frequency is doubled. In this case, the control means shifts the pulse 28a in the time base direction so that the pulse appears earlier than the signal VS by a prescribed horizontal period. Since distortion due to a skew signal is included in an over scan region and does not appears on the effective picture screen, the video signal due to the skew signal is not distorted.

5. 发明专利

JPH02143777A VIDEO SIGNAL PROCESSING UNIT 失效
公开(公告)号：JPH02143777A
公开(公告)日：1990-06-01
申请号：JP29784988
申请日：1988-11-25
申请人： SONY CORP
发明人： NAITO HIDEFUMI , SARUGAKU TOSHIO , TOKUHARA MASAHARU
IPC分类号： H04N5/06 , H04N9/44
摘要： PURPOSE:To prevent production of vertical jitter due to a clock signal when a vertical synchronizing signal pulse is formed from a vertical synchronizing signal separated from a video signal by using 1st and 2nd latch pulses so as to latch a vertical synchronizing signal at a specific time. CONSTITUTION:When an initial point of a vertical synchronizing signal enters a window period of a 1st window signal 18a, a 2nd latch pulse 19b is used to latch a vertical synchronizing signal Vs and when the first point of the vertical synchronizing signal Vs enters a window period of a 2nd window signal 18b, a 1st latch pulse 19a is used to latch the vertical synchronizing signal Vs to obtain a vertical synchronizing pulse. Thus, the production of vertical jitter by a clock signal is not caused when the vertical synchronizing pulse is generated from the vertical synchronizing signal is separated from the video signal.

6. 发明专利

JPH0289477A FLICKER REDUCTION DEVICE 失效
公开(公告)号：JPH0289477A
公开(公告)日：1990-03-29
申请号：JP24136588
申请日：1988-09-27
申请人： SONY CORP
发明人： NAITO HIDEFUMI , SARUGAKU TOSHIO , TOKUHARA MASAHARU
IPC分类号： H04N5/92 , H04N5/93 , H04N5/937
摘要： PURPOSE:To reduce flicker of a VTR picture without deteriorating the quality of a picture even if number of horizontal scanning lines is fluctuated by writing a video signal in a storage means with a larger capacity than that of an effective pattern while inhibiting the write as required and reading out the signal at a double speed at that of the write while similarly inhibiting readout as required similarly. CONSTITUTION:The length of a write control signal from a flicker reduction circuit 29 is detected by a write period length detection circuit 1, compared with a reference value and if the number of horizontal synchronizing signal for a vertical synchronizing signal is number of capacity or over of a field memory 28 larger in capacity than that of the effective pattern, the write of a video data to the memory 26 is inhibited via a comparator circuit 3 and a Write enable signal generation inhibit circuit 6. The readout of the data is implemented at a double speed of the write speed while being inhibited similarly as required and fed to a display section, the flicker is reduced and even if the number of horizontal synchronizing signals for the vertical synchronizing signal is fluctuated at special reproduction of a VTR, the deterioration of the quality of picture is prevented.

7. 发明专利

JPH0281596A VIDEO SIGNAL PROCESSOR 失效
公开(公告)号：JPH0281596A
公开(公告)日：1990-03-22
申请号：JP23325588
申请日：1988-09-17
申请人： SONY CORP
发明人： NAITO HIDEFUMI , SARUGAKU TOSHIO , HOSHINO TAKANARI , TOKUHARA MASAHARU
IPC分类号： H04N5/21 , H04N5/93 , H04N9/80 , H04N9/804 , H04N9/808 , H04N11/20
摘要： PURPOSE:To simplify a system by using a memory means for both noise reduction means, which eliminates noise with the use of the correlation of the field of a video signal, and flicker reduction means, which doubles field frequencies and decreases a surface flicker. CONSTITUTION:A noise reduction circuit 22 is made into a circulative type filter constitution, and it is repeatedly added with the use of a single filter memory 26. In the field memory 26, the signal is written by a write control signal VCLRO from a flicker reduction circuit 29, digital luminance data read and added by a read control signal VCLR2 are generally outputted through a digital/analog converting circuit 30 after noise reduction. The field memory 26 used for the noise reduction circuit 22 is shared with the field memory of the flicker reduction circuit 29. Thus, the whole system can be simplified, and costs can be reduced.

8. 发明专利

JPH0229171A VIDEO SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPH0229171A
公开(公告)日：1990-01-31
申请号：JP17962088
申请日：1988-07-19
申请人： SONY CORP
发明人： MOTOE HISASHI , KAWASHIMA HIROYUKI , TOKUHARA MASAHARU
IPC分类号： H04N5/14 , H04N5/21
摘要： PURPOSE:To suppress dot disturbance without any inconvenience by inserting a filter to eliminate a chrominance signal component into a signal line for animation data when a vertical edge is to be detected by a vertical edge detector. CONSTITUTION:In the title signal processing circuit to form both still picture data and the animation data from a luminance signal Y separated in a Y/C separating circuit composed of a tandem filter using line correlation and execute processing for obtaining high picture quality such as scanning line incorporation, the signal processing circuit is equipped with a vertical edge detector 519 and filters 515 and 516 to eliminate the chrominance signal component, and when the vertical edge is to be detected, the filters 515 and 516 to eliminate the chrominance signal component are inserted into the signal line for the animation data. Consequently, the chrominance signal component included in the animation data is eliminated correspondingly to a vertical edge part. Thus, the dot disturbance can be suppressed without any inconvenience.

9. 发明专利

JPH0229170A VIDEO SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPH0229170A
公开(公告)日：1990-01-31
申请号：JP17961888
申请日：1988-07-19
申请人： SONY CORP
发明人： MOTOE HISASHI , MOTOMIYA MASAYUKI , KAWASHIMA HIROYUKI , TOKUHARA MASAHARU
IPC分类号： H04N5/14
摘要： PURPOSE:To minimize a circuit scale and to execute satisfactory Y/C separation and high picture quality processing all the time by providing an analog Y/C separating circuit, supplying a clock phase-locked with a horizontal synchronizing signal, and executing processing such as scanning line interpolation. CONSTITUTION:A luminance signal Y outputted from a Y/C separating circuit 2 is converted into a digital signal in an A/D converter 3Y and after that supplied to a signal processing circuit 5Y, a chrominance signal C is color- demodulated in a chroma decoder 4, converted into the digital signal in an A/D converter 3C, and after that supplied to a signal processing circuit 5C, signal processing such as the scanning line interpolation is executed, and both the luminance signal Y and the chrominance signal C are respectively made into analog signals in D/A converters 6Y, 6R and 6B. Further, a clock CLKH phase-locked with a horizontal synchronizing signal HD is outputted from a generating circuit 7, and this clock CLKH is supplied to a digital processing system composed from the A/D converters 3Y and 3C to the D/A converters 6Y, 6R and 6B. Thus, the circuit scale can be minimized, and the satisfactory Y/C separation and the processing for obtaining high picture quality can be executed all the time.

10. 发明专利

JPS6446375A PICTURE SIGNAL PROCESSOR 失效
公开(公告)号：JPS6446375A
公开(公告)日：1989-02-20
申请号：JP20264087
申请日：1987-08-14
申请人： SONY CORP
发明人： SONODA YUTAKA , YUJI HIROFUMI , MURAKAMI KYOICHI , TOKUHARA MASAHARU
IPC分类号： H04N5/262 , G09G5/399 , H04N5/45 , H04N5/907
摘要： PURPOSE:To prevent the turblence of a picture from being generated due to a passing phenomenon by separating a reading address or a writing frame for the unit of frames or fields when the reading address and the writing address mutually pass. CONSTITUTION:An image memory 13 have memory capacity equivalent to four frames or for frames more than four to which an access is successively executed in a prescribed order. It is detected by passing detecting means 42 and 43 that a condition, in which the frame read by a reading address signal RADR and the frame written by a writing address signal WADR are mutually adjoined, is obtained. In correspondence to detecting outputs S21 and S22 of these passing detecting means 42 and 43, the writing address designated by the writing address signal WADR or the reading address designated by the reading address signal RADR is separated for one frame or plural frames by address separating means 41 and 44. Thus, the turbulence on the display image is prevented from being generated.

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