专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2005332545A Data encoding circuit, data encoding method, and data recording apparatus 审中-公开
标题翻译：数据编码电路，数据编码方法和数据记录装置
公开(公告)号：JP2005332545A
公开(公告)日：2005-12-02
申请号：JP2004152518
申请日：2004-05-21
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： OKAMOTO SANEYUKI , FUMA MASATO , TOMIZAWA SHINICHIRO , NORO SATOSHI , SENOO HIDEMITSU
IPC分类号： G11B20/12 , G11B20/10 , G11B20/18 , H03M13/00
CPC分类号： G11B20/1833 , G11B20/1866 , G11B2020/184
摘要： PROBLEM TO BE SOLVED: To provide a data encoding circuit, a data encoding method, and a data recording apparatus which can secure the real time performance of recording operation even by a memory low in dynamic clock by reducing the number of times of accessing a memory, amd also can make low in power consumption and the price of the memory.
SOLUTION: Before data from a host is written in a memory 101, it is inputted to an EDC arithmetic circuit 110 and a scramble arithmetic circuit 111 and processed, after that, additional processing of an error correction code is performed by a PI arithmetic circuit 104 and a PO arithmetic circuit 105 for data written in the memory 101 from the scramble arithmetic circuit 111. memory access when data is written in the memory from the host and memory access when data is read out to the EDC arithmetic circuit from the memory can be eliminated. Thereby, the dynamic clock of the memory 101 can be reduced.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种数据编码电路，数据编码方法和数据记录装置，即使通过低动态时钟的存储器也能够保证记录操作的实时性能，通过减少动态时钟的次数访问内存时，amd也可以降低功耗和内存的价格。解决方案：在将来自主机的数据写入存储器101之前，将其输入到EDC运算电路110和加扰运算电路111，然后进行处理，之后由PI执行纠错码的附加处理算术电路104和PO运算电路105，用于从加扰运算电路111写入存储器101的数据。当数据从主机写入存储器时的存储器访问和存储器存取时，当数据从记忆可以消除。由此，可以减少存储器101的动态时钟。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2005332543A Data encoding circuit, data encoding method, and data recording apparatus 审中-公开
标题翻译：数据编码电路，数据编码方法和数据记录装置
公开(公告)号：JP2005332543A
公开(公告)日：2005-12-02
申请号：JP2004152516
申请日：2004-05-21
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： OKAMOTO SANEYUKI , FUMA MASATO , TOMIZAWA SHINICHIRO , NORO SATOSHI , SENOO HIDEMITSU
IPC分类号： G11B20/14 , G06F11/10 , G11B20/12 , G11B20/18 , H03M13/00
CPC分类号： G11B20/1866 , G11B20/1833 , G11B2020/184
摘要： PROBLEM TO BE SOLVED: To provide a data encoding circuit, a data encoding method, and a data recording apparatus which can secure the real time property of recording operation even by a memory low in dynamic clock by reducing the number of times of access to a memory, and can make power consumption low and the cost of the memory low simultaneously.
SOLUTION: Before data from a host is written in a memory 101, processing is performed by an EDC arithmetic circuit 110 and a scramble arithmetic circuit 111 and it is written in the memory 101. Next, error correction encoding processing of a PO direction is performed by a PO arithmetic circuit 105, the obtained PO code is written in the memory 101 so as to add to corresponding data. After that , data in the memory 101 is read out to a PI arithmetic circuit 110 in the PI direction every one line, a PI code is added to this and the data is outputted successively to a modulation circuit 200. Thereby, the number of access for the memory 101 can be reduced remarkably, a dynamic clock of the memory 101 can be reduced.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种数据编码电路，数据编码方法和数据记录装置，即使通过动态时钟低的存储器也能够确保记录操作的实时性，通过减少动态时钟的次数访问存储器，并且可以使功耗低，并且存储器的成本同时低。解决方案：在来自主机的数据被写入存储器101之前，由EDC运算电路110和加扰运算电路111进行处理，并将其写入存储器101.接下来，PO的纠错编码处理方向由PO运算电路105执行，将获得的PO代码写入存储器101，以便添加到相应的数据。之后，将存储器101中的数据每PI行向PI运算电路110读出，向该调制电路200连续地输出PI代码，从而将数据存入可以显着地减少存储器101的可用性，可以减少存储器101的动态时钟。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2005174550A Data processor 审中-公开
标题翻译：数据处理器
公开(公告)号：JP2005174550A
公开(公告)日：2005-06-30
申请号：JP2005038131
申请日：2005-02-15
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： TOMIZAWA SHINICHIRO , NORO SATOSHI , HIDETOKU TOSHIYUKI , SHIRAISHI TAKUYA , NAGAI HIROKI
IPC分类号： G11B20/14 , G11B20/10 , G11B20/18
摘要： PROBLEM TO BE SOLVED: To provide a data processor capable of suppressing an increase in a circuit scale.
SOLUTION: The data processor is an LSI with the functions of decoders and encoders integrated in one chip, and is built in a recording and reproducing device capable of treating a CD and DVD as a recording medium. In the data processor, an 8-16 modulation circuit 32 and an EFM modulation circuit 42 operate in time-division manner according to the kind of a disk set on the recording and reproducing device. A write strategy circuit 27 generates a pulse signal for driving laser in response to a modulated data outputted from a modulation circuit under operation.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供能够抑制电路规模增加的数据处理器。解决方案：数据处理器是具有集成在一个芯片中的解码器和编码器的功能的LSI，并且内置在能够将CD和DVD作为记录介质处理的记录和再现装置中。在数据处理器中，8-16调制电路32和EFM调制电路42根据在记录和再现装置上设置的盘的种类以时分方式进行操作。写策略电路27响应于在操作中的调制电路输出的调制数据，产生用于驱动激光的脉冲信号。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2004159161A Delay signal generation device and write pulse generation device 审中-公开
标题翻译：延迟信号发生装置和写脉冲发生装置
公开(公告)号：JP2004159161A
公开(公告)日：2004-06-03
申请号：JP2002323785
申请日：2002-11-07
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： HIDETOKU TOSHIYUKI , TOMIZAWA SHINICHIRO
IPC分类号： G11B20/10 , G11B7/0045 , G11B7/006 , G11B7/125 , G11B20/14 , H03K5/00 , H03K5/13 , H03L7/08 , H03L7/081 , H03L7/099 , H03L7/18 , H04L7/033
CPC分类号： G11B7/126 , G11B7/00456 , G11B7/0062 , G11B20/10 , H03K5/133 , H03K2005/00039 , H03L7/0805 , H03L7/0995 , H03L7/18 , H04L7/0337
摘要： PROBLEM TO BE SOLVED: To favorably suppress increase in the size of a circuit even when a plurality of delay signals, in which a minimum unit of the delay amount is different from one another, are generated for one input signal.
SOLUTION: Based on data modulated with a DVD encoder or a CD encoder, a write pulse which controls an output of a laser irradiated on an optical disc is generated. The write pulse is generated by logically synthesizing delay signals D1-D4 provided by respectively delaying signals to be delayed S1-S4 at each delay circuit 220 whose delay amount is controlled by a delay amount control circuit 210 at a logic circuit 300. In the delay amount control circuit 210, an output signal of a voltage controlled oscillator 211 is constituted by connecting a plurality of stages of delay elements 211a having the same constitution as each delay element 221 of the delay circuit 220 in ring-form, and is locked at a position where the delay amount of the delay element 211a becomes integer-th part of a single period of a reference clock.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：即使对于一个输入信号产生延迟量的最小单位彼此不同的多个延迟信号，也有利地抑制电路尺寸的增加。解决方案：基于用DVD编码器或CD编码器调制的数据，产生控制在光盘上照射的激光器的输出的写入脉冲。写入脉冲是通过逻辑合成延迟信号D1-D4产生的，延迟信号D1-D4分别延迟每个延迟电路220延迟S1-S4的信号，延迟量由延迟量控制电路210在逻辑电路300处控制。在延迟数量控制电路210，压控振荡器211的输出信号通过将具有与延迟电路220的每个延迟元件221具有相同结构的多级延迟元件211a连接成环状而构成，并被锁定在延迟元件211a的延迟量变为参考时钟的单个周期的整数部分的位置。版权所有（C）2004，JPO

5. 发明专利

JP2003338141A Data reproduction controller 审中-公开
标题翻译：数据再生控制器
公开(公告)号：JP2003338141A
公开(公告)日：2003-11-28
申请号：JP2002142969
申请日：2002-05-17
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： NAGAI HIROKI , TOMIZAWA SHINICHIRO
IPC分类号： G06F11/10 , G11B20/10 , G11B20/18 , H03M13/29
CPC分类号： G11B20/1833 , G11B2020/1062
摘要： PROBLEM TO BE SOLVED: To provide a data reproduction controller which enables the reproducer of data recorded on a recording medium such as a DVD (digital versatile disk) with an error-correcting code to perform a faster reproducing operation.
SOLUTION: A PI (inner code parity) correcting circuit 21 performs the error-correcting processing of the PI and also starts up a completion signal CT every time when the processing for data equivalent to 182 bytes is completed. A counter circuit 26 counts the completion signal CT to increment successively a count value CO every time the completion signal CT is started up. A decision circuit 27 compares the count value CO with a prescribed set value K and decides whether data to which the error-correcting processing of the PI is completed are rows of a PO (outer code parity) or not based on the compared result. When the circuit 27 judges the data to be the rows of the PO, the circuit 27 starts up a first control signal S1 and it gives an instruction to a descramble circuit 23 so as not perform scrambling processing to the data which are judged to be the rows of the PO.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种数据再现控制器，其使得记录在具有纠错码的DVD（数字通用盘）等记录介质上的数据的再现器能够执行更快的再现操作。解决方案：PI（内码奇偶校验）校正电路21执行PI的纠错处理，并且每当完成等同于182字节的数据的处理时，也启动完成信号CT。计数器电路26对完成信号CT进行计数，以在每次完成信号CT启动时连续递增计数值CO。判定电路27将计数值CO与规定的设定值K进行比较，并且基于比较结果来判定PI的纠错处理的数据是否完成PO（外码奇偶校验）的行。当电路27将数据判断为PO的行时，电路27启动第一控制信号S1，并向解密电路23发出指令，以便对被判断为是 PO的行。版权所有（C）2004，JPO

6. 发明专利

JP2003272144A Data processing apparatus 审中-公开
标题翻译：数据处理设备
公开(公告)号：JP2003272144A
公开(公告)日：2003-09-26
申请号：JP2002071324
申请日：2002-03-15
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： TOMIZAWA SHINICHIRO , NORO SATOSHI , HIDETOKU TOSHIYUKI , SHIRAISHI TAKUYA , NAGAI HIROKI
IPC分类号： G11B20/10 , G11B7/00 , G11B7/004 , G11B7/0045 , G11B7/005 , G11B7/006 , G11B20/14
CPC分类号： G11B20/1403 , G11B7/00456 , G11B7/005 , G11B7/0062 , G11B2007/0006 , G11B2020/10879
摘要： PROBLEM TO BE SOLVED: To provide a data processing apparatus the increase in the circuit scale of which can be suppressed.
SOLUTION: The data processing apparatus is an LSI for integrating functions of a decoder and an encoder into one chip and assembled in a recording and reproducing apparatus capable of processing a CD and a DVD as recording media. A 8-16 modulation circuit 32 and an EFM modulation circuit 42 in the data processing apparatus are operated in time division depending on a type of a disk set to the recording and reproducing apparatus. A write strategy circuit 27 receives modulation data outputted from the modulation circuit in operation and generates a pulse signal to drive a laser.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：为了提供可以抑制其电路规模的增加的数据处理装置。解决方案：数据处理装置是用于将解码器和编码器的功能集成为一个芯片并组装在能够处理CD和DVD作为记录介质的记录和再现装置中的LSI。数据处理装置中的8-16调制电路32和EFM调制电路42根据设置到记录和再现装置的盘的类型进行时分运算。写入策略电路27在操作中接收从调制电路输出的调制数据，并产生用于驱动激光的脉冲信号。版权所有（C）2003，JPO

7. 发明专利

JP2006309820A Error correction device 审中-公开
标题翻译：错误校正装置
公开(公告)号：JP2006309820A
公开(公告)日：2006-11-09
申请号：JP2005128053
申请日：2005-04-26
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： TOMIZAWA SHINICHIRO
IPC分类号： G11B20/18 , H03M13/29
CPC分类号： G11B20/1809 , G11B20/10527 , G11B2020/1062 , G11B2020/10759 , H03M13/1515 , H03M13/2909 , H03M13/293
摘要： PROBLEM TO BE SOLVED: To efficiently perform the error correction processing of a block code constituted by combining at least two sets of error correction codes and to suppress the increase of a circuit scale.
SOLUTION: This error correction device for performing the error correction of the block code constituted by imparting first and second error correction codes comprises: a syndrome operation part for performing a syndrome operation based on the first error correction code by a row unit in parallel with the storage of the received block code in a buffer memory and generating the discriminated result of the presence/absence of the error of each row; a buffering part for buffering the discriminated result; and a correction processing part for performing the correction processing on the basis of the second error correction code of each column of the block code read from the buffer memory and the buffered discriminated result. Alternatively, the buffering part is replaced with a buffer transfer part for transferring the discriminated result generated in the syndrome operation part to the buffer memory and a buffering part for reading the discriminated result from the buffer memory and buffering it.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了有效地执行通过组合至少两组纠错码而构成的块码的纠错处理，并抑制电路规模的增加。解决方案：用于执行通过施加第一和第二纠错码构成的块码的纠错的纠错装置包括：校正子操作部分，用于基于第一纠错码通过行单元执行校正子操作并行地将接收的块码存储在缓冲存储器中，并产生各行存在/不存在错误的鉴别结果; 用于缓冲所识别的结果的缓冲部分; 以及校正处理部分，用于基于从缓冲存储器读取的块码的每列的第二纠错码和缓冲的鉴别结果来执行校正处理。或者，将缓冲部分替换为用于将在校正子操作部分中产生的鉴别结果传送到缓冲存储器的缓冲器传送部分和用于从缓冲存储器读取鉴别结果并缓冲它的缓冲部件。版权所有（C）2007，JPO＆INPIT

8. 发明专利

JP2006092042A Information processor and context switching method 审中-公开
标题翻译：信息处理器和语境切换方法
公开(公告)号：JP2006092042A
公开(公告)日：2006-04-06
申请号：JP2004274219
申请日：2004-09-21
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： TOMIZAWA SHINICHIRO
IPC分类号： G06F9/48
CPC分类号： G06F9/462
摘要： PROBLEM TO BE SOLVED: To provide an information processor suitable for a real time system and its context switching method.
SOLUTION: This information processor for making a processor simultaneously execute a plurality of processing units in parallel by switching contexts corresponding to each processing unit at the time of making the processor execute the plurality of predetermined processing units is provided with: a plurality of register banks for respectively storing the contexts associated with each of the plurality of processing units, the processor for performing processing corresponding to foreground contexts at the time of switching contexts, and a save/restore controller for saving background contexts in a memory, and for restoring the contexts of the processing units to be executed the next from the memory in a background register bank in parallel with the execution of the processing corresponding to the foreground contexts in the processor.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供适合于实时系统的信息处理器及其上下文切换方法。解决方案：用于使处理器通过在处理器执行多个预定处理单元时对应于每个处理单元的切换上下文并行执行多个处理单元的该信息处理器具有：多个寄存器组，用于分别存储与多个处理单元中的每一个相关联的上下文，用于在切换上下文时执行与前景上下文相对应的处理的处理器，以及用于将后台上下文保存在存储器中并用于恢复的保存/恢复控制器与后处理单元中的前台上下文相对应的处理的执行并行执行的下一个处理单元的上下文将在后台寄存器组中的存储器中执行。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2004087027A Access circuit 审中-公开
标题翻译：访问电路
公开(公告)号：JP2004087027A
公开(公告)日：2004-03-18
申请号：JP2002248716
申请日：2002-08-28
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： NORO SATOSHI , TOMIZAWA SHINICHIRO
IPC分类号： G06F12/04 , G06F3/06 , G06F12/00 , G11B20/10 , G11C7/00 , G11C7/10 , G11C8/00 , G11C11/408 , G11C11/4096
CPC分类号： G11C7/1006 , G11C11/4082 , G11C11/4096
摘要： PROBLEM TO BE SOLVED: To provide an access circuit in which a time required for accessing a buffer memory can be reduced suitably in accordance with indication from the outside.
SOLUTION: In a control unit 20, a data unit specifying signal specifying any one out of one byte, one word, and two words as access data quantity for accessing a SDRAM 10 in one period of an operation clock of an access circuit is outputted to an address decoder 110 as address data. And a request generating section 130 outputs a request signal indicating access with this data quantity based on the access data quantity decoded by an address decoder 110. And a memory interface 140 accesses the SDRAM 10 with access data quantity in accordance with indication of the request signal from this specified address when the head address of data accessing the SDRAM 10 is specified from the outside.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种访问电路，其中可以根据来自外部的指示适当地减少访问缓冲存储器所需的时间。解决方案：在控制单元20中，指定访问电路的操作时钟的一个周期中的一个字节，一个字和两个字中的任一个的数据单元指定信号作为访问SDRAM 10的访问数据量作为地址数据输出到地址解码器110。另外，请求生成部130基于由地址解码器110解码的访问数据量，输出表示具有该数据量的访问的请求信号。存储器接口140根据请求信号的指示访问具有访问数据量的SDRAM10 当从外部指定访问SDRAM 10的数据的头地址时，从该指定地址。版权所有（C）2004，JPO

10. 发明专利

JP2004039131A Code error correction device 审中-公开
公开(公告)号：JP2004039131A
公开(公告)日：2004-02-05
申请号：JP2002195975
申请日：2002-07-04
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： NAGAI HIROKI , TOMIZAWA SHINICHIRO
IPC分类号： G11B20/18 , H03M13/29 , H03M13/35
摘要： PROBLEM TO BE SOLVED: To provide a code error correction device that corrects a code error of data to which an error correction code is added and which is recorded in a recording medium and that realizes a high speed reproduction operation while securing the reliability.
SOLUTION: A PI correction processing circuit 20 and a PO correction processing circuit 25 repeat an error correction processing for certain times on an inner parity PI and an outer parity PO of data for one block, which is read from DRAM 18. A detection processing circuit 23 detecting the error detects the error of data to which the PI or PO error correction processing is performed. A control circuit 31 stores data which is read from DVD in DRAM 18 based on a synchronizing signal and performs the PI and PO error correction processing in asynchronizing with a buffering processing. When the data error is eliminated as a result of an error detection processing, the error correction processing is terminated.
COPYRIGHT: (C)2004,JPO

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式