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    • 1. 发明专利
    • Cmos element with improved performance, and manufacturing method of the same
    • 具有改进性能的CMOS元件及其制造方法
    • JP2006049903A
    • 2006-02-16
    • JP2005223255
    • 2005-08-01
    • Samsung Electronics Co Ltd三星電子株式会社Samsung Electronics Co.,Ltd.
    • JUNG MU-KYENGKANG HEE-SUNGRYU HYUK-JUCHUNG WOO-YOUNGKIN KEISHU
    • H01L21/8238H01L21/76H01L27/08H01L27/092H01L29/78
    • H01L29/7846H01L21/823814H01L21/82385H01L29/7833H01L29/7843
    • PROBLEM TO BE SOLVED: To provide a CMOS element whose performance is improved, and to provide a manufacturing method of the same.
      SOLUTION: A CMOS element comprises a first active region, including a first width range and at least one of multiple width active region pair, having a second width range larger than the first width range becoming a contact forming region; a first conductive type MOS transistor, including a first gate arranged on the first active region and a first conductivity-type source/drain region formed in the first active region; and a second conductivity-type MOS transistor, including a second active region having a third width range larger than the first width range, a second gate arranged on the second active region, and a second conductive type source/drain region formed on the second active region. In addition, a manufacturing method of the CMOS element is provided. Accordingly, a performance of the CMOS element is improved and balance between mobility of electrons and positive holes is obtained.
      COPYRIGHT: (C)2006,JPO&NCIPI
    • 要解决的问题:提供性能提高的CMOS元件,并提供其制造方法。 解决方案:CMOS元件包括第一有源区,包括第一宽度范围和多宽度有源区对中的至少一个,具有大于第一宽度范围的第二宽度范围成为接触形成区域; 第一导电型MOS晶体管,包括布置在第一有源区上的第一栅极和形成在第一有源区中的第一导电型源/漏区; 以及第二导电型MOS晶体管,包括具有大于第一宽度范围的第三宽度范围的第二有源区,布置在第二有源区上的第二栅极和形成在第二有源区上的第二导电型源极/漏极区 地区。 另外,提供了CMOS元件的制造方法。 因此,提高了CMOS元件的性能,并且获得了电子和空穴的迁移率之间的平衡。 版权所有(C)2006,JPO&NCIPI