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1. 发明专利

JP2007049148A Semiconductor element provided with barrier metal spacer and its manufacturing method 有权
标题翻译：带有隔离金属间隔器的半导体元件及其制造方法
公开(公告)号：JP2007049148A
公开(公告)日：2007-02-22
申请号：JP2006214517
申请日：2006-08-07
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： LEE BOUNG JU , SHIN HEON-JONG , KANG HEE-SUNG
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L21/76832 , H01L21/02063 , H01L21/76805 , H01L21/76807 , H01L21/76814 , H01L21/76834 , H01L21/76844 , H01L21/76846 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor element provided with a barrier metal spacer, and its manufacturing method. SOLUTION: A semiconductor element is provided with: a first metal line formed in a semiconductor substrate; an etch stop film provided with a via plug that is electrically connected with a part of the first metal line and containing a window; an interlayer insulating film comprising a via hole and a trench; and a first barrier metal spacer covering the sidewall of the interlayer insulating film in the via hole, to expose a part of the first metal line and at least the lower end of the sidewall of the etch stop film in the window. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种设置有阻挡金属间隔物的半导体元件及其制造方法。解决方案：半导体元件设置有：形成在半导体衬底中的第一金属线; 设置有与第一金属线的一部分电连接并且包含窗口的通孔塞的蚀刻停止膜; 包括通孔和沟槽的层间绝缘膜; 以及覆盖所述通孔中的所述层间绝缘膜的侧壁的第一阻挡金属间隔件，以暴露所述第一金属线的一部分和所述窗口中所述蚀刻停止膜的侧壁的至少下端。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2006049903A Cmos element with improved performance, and manufacturing method of the same 审中-公开
标题翻译：具有改进性能的CMOS元件及其制造方法
公开(公告)号：JP2006049903A
公开(公告)日：2006-02-16
申请号：JP2005223255
申请日：2005-08-01
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： JUNG MU-KYENG , KANG HEE-SUNG , RYU HYUK-JU , CHUNG WOO-YOUNG , KIN KEISHU
IPC分类号： H01L21/8238 , H01L21/76 , H01L27/08 , H01L27/092 , H01L29/78
CPC分类号： H01L29/7846 , H01L21/823814 , H01L21/82385 , H01L29/7833 , H01L29/7843
摘要： PROBLEM TO BE SOLVED: To provide a CMOS element whose performance is improved, and to provide a manufacturing method of the same.
SOLUTION: A CMOS element comprises a first active region, including a first width range and at least one of multiple width active region pair, having a second width range larger than the first width range becoming a contact forming region; a first conductive type MOS transistor, including a first gate arranged on the first active region and a first conductivity-type source/drain region formed in the first active region; and a second conductivity-type MOS transistor, including a second active region having a third width range larger than the first width range, a second gate arranged on the second active region, and a second conductive type source/drain region formed on the second active region. In addition, a manufacturing method of the CMOS element is provided. Accordingly, a performance of the CMOS element is improved and balance between mobility of electrons and positive holes is obtained.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供性能提高的CMOS元件，并提供其制造方法。解决方案：CMOS元件包括第一有源区，包括第一宽度范围和多宽度有源区对中的至少一个，具有大于第一宽度范围的第二宽度范围成为接触形成区域; 第一导电型MOS晶体管，包括布置在第一有源区上的第一栅极和形成在第一有源区中的第一导电型源/漏区; 以及第二导电型MOS晶体管，包括具有大于第一宽度范围的第三宽度范围的第二有源区，布置在第二有源区上的第二栅极和形成在第二有源区上的第二导电型源极/漏极区地区。另外，提供了CMOS元件的制造方法。因此，提高了CMOS元件的性能，并且获得了电子和空穴的迁移率之间的平衡。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2004311999A Method of fabricating semiconductor element having shallow source/drain regions 审中-公开
标题翻译：制造具有深源/漏区的半导体元件的方法
公开(公告)号：JP2004311999A
公开(公告)日：2004-11-04
申请号：JP2004101507
申请日：2004-03-30
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： LEE SANG-JIN , KIN KEISHU , GO SHOHO , KANG HEE-SUNG
IPC分类号： H01L21/265 , H01L21/336 , H01L29/78 , H01L29/786
CPC分类号： H01L29/6653 , H01L21/2652 , H01L21/26586 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： PROBLEM TO BE SOLVED: To provide a method of fabricating a semiconductor element having shallow source/drain regions. SOLUTION: First spacers are formed on insulating layers on both sidewalls of each gate pattern. Deep source/drain regions are formed in the semiconductor substrate of interest so as to align with the first spacers. After removing the first spacers, the insulating layers are etched to form second spacers for offsetting on both of the sidewalls of each gate pattern. Shallow source/drain regions are formed in the regions of the semiconductor substrate aligned with the second spacers for offsetting and adjoining the deep source/drain regions. Thus, it is realized to form the deep source/drain regions prior to the shallow source/drain regions, and to control an overlap of the impurities ion-implanted into the shallow source/drain regions created through the gate pattern line width gradually reducing with the second spacer for offsetting. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种制造具有浅源/漏区的半导体元件的方法。解决方案：在每个栅极图案的两个侧壁上的绝缘层上形成第一间隔物。在感兴趣的半导体衬底中形成深源极/漏极区，以便与第一间隔物对准。在去除第一间隔物之后，蚀刻绝缘层以形成用于在每个栅极图案的两个侧壁上偏移的第二间隔物。在与第二间隔物对准的半导体衬底的区域中形成浅源极/漏极区，用于抵消和邻接深源极/漏极区。因此，实现了在浅源/漏区之前形成深源/漏区，并且控制离子注入到通过栅极图案线宽度产生的浅源/漏区中的杂质的重叠逐渐减小，用于抵消的第二间隔件。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2003318283A Semiconductor element using silicon germanium gate and method for manufacturing the same 有权
标题翻译：使用硅锗门的半导体元件及其制造方法
公开(公告)号：JP2003318283A
公开(公告)日：2003-11-07
申请号：JP2003080765
申请日：2003-03-24
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： RYU HYUK-JU , KIM YOUNG-WUG , GO SHOHO , KANG HEE-SUNG
IPC分类号： H01L21/28 , H01L21/306 , H01L21/3065 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49
CPC分类号： H01L27/092 , H01L21/823842
摘要： PROBLEM TO BE SOLVED: To provide a CMOS semiconductor element using a silicon germanium gate and a method for manufacturing it.
SOLUTION: A gate insulating film, a conductive electrode film with selective film quality, a silicon germanium electrode film and a conductive amorphous electrode film are successively formed on a semiconductor substrate so that a silicon germanium electrode film can be formed only in a PMOS area, and not formed in an NMOS area. Afterwards, the silicon germanium electrode film in the NMOS area is removed through a photo-etching process, and the silicon germanium electrode film is made to remain only in the PMOS area.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供使用硅锗栅的CMOS半导体元件及其制造方法。解决方案：在半导体衬底上依次形成栅极绝缘膜，具有选择性膜质量的导电电极膜，硅锗电极膜和导电非晶电极膜，从而可以仅形成硅锗电极膜 PMOS区域，并且不形成在NMOS区域中。之后，通过光蚀刻工艺去除NMOS区域中的硅锗电极膜，并使硅锗电极膜仅保留在PMOS区域中。版权所有（C）2004，JPO

5. 发明专利

JP2003282738A Sram memory cell and its manufacturing method 有权
标题翻译： SRAM存储单元及其制造方法
公开(公告)号：JP2003282738A
公开(公告)日：2003-10-03
申请号：JP2003067914
申请日：2003-03-13
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： JUNG MU-KYENG , KIM YOUNG-WUG , KANG HEE-SUNG
IPC分类号： H01L21/8244 , H01L21/84 , H01L27/11 , H01L27/12 , H01L29/786
CPC分类号： H01L27/11 , H01L21/84 , H01L27/1104 , H01L27/1203
摘要： PROBLEM TO BE SOLVED: To provide an SRAM memory cell in which a floating effect occurring when an SOI substrate is used and to provide a method for manufacturing the same.
SOLUTION: The method for manufacturing the SRAM memory cell comprises a step of coupling a floated body of an access transistor AT of the SRAM to a source region of a driver transistor DT via a body extended part formed by extending an active region. Thus, a passivation effect is prevented. An undesired pn junction formed between the body extended part and the source region of the driver transistor is electrically coupled by forming a silicide or overetching a VSS contact to form a conductive contact plug.
COPYRIGHT: (C)2004,JPO
摘要翻译：解决的问题：提供一种SRAM存储单元，其中使用SOI衬底时产生浮动效应并提供其制造方法。解决方案：用于制造SRAM存储单元的方法包括通过经由延伸有源区形成的主体延伸部分将SRAM的存取晶体管AT的浮体耦合到驱动晶体管DT的源极区的步骤。因此，防止钝化效果。形成在驱动晶体管的主体延伸部分和源极区域之间的不期望的pn结通过形成硅化物或过蚀刻VSS触点而电耦合以形成导电接触插塞。版权所有（C）2004，JPO

6. 发明专利

JP2002353467A SOI SEMICONDUCTOR DEVICE AND FORMING METHOD THEREFOR 审中-公开
公开(公告)号：JP2002353467A
公开(公告)日：2002-12-06
申请号：JP2002096787
申请日：2002-03-29
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： LEE NAE-IN , LEE INHI , KANG HEE-SUNG , BAE GEUM-JONG
IPC分类号： H01L21/76 , H01L21/762 , H01L27/08 , H01L27/12 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide an SOI semiconductor device, and a forming method therefor. SOLUTION: On an SOI type wafer, a shallow trench is formed in a connecting part as one part of a device isolation film-forming area between a device region and a ground area by utilizing an etching-proof film. An impurity layer is formed on the base of the shallow trench. On the remaining part, except for the intermediate connecting part of the device isolation film forming area between the device region and the ground region, a deep trench for exposing an embedded oxide layer is formed by utilizing an etching-proof film pattern. Then, a device isolating film is formed by filling a wafer, which has shallow and deep trenches with an insulation film. In a step for forming the impurity layer on the base of the shallow trench, a method for forming the monocrystal epitaxial layer of silicon-germanium on the silicon base of the exposed shallow trench is available. Also a method for ion implantation of germanium or argon can be used.

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