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1. 发明专利

JP2007173833A Asymmetric semiconductor device and its manufacture method 审中-公开
标题翻译：不对称半导体器件及其制造方法
公开(公告)号：JP2007173833A
公开(公告)日：2007-07-05
申请号：JP2006344550
申请日：2006-12-21
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： CHANG CHANSAM , MAEDA SHIGENOBU , GO SHOHO , SHIN HEON-JONG
IPC分类号： H01L21/8234 , H01L21/76 , H01L21/8238 , H01L27/08 , H01L27/088 , H01L27/092
CPC分类号： H01L21/823892 , H01L21/823814 , H01L27/0928
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device reduced in the number of process stages and having high-voltage and low-voltage transistors on the same substrate, and its manufacturer method.
SOLUTION: In a CMOS integrated circuit characterized by comprising high-voltage asymmetric NMOS, PMOS and low-voltage NMOS, PMOS separated by separation regions having a first depth in the substrate, first dopants are injected to a second depth in the drain region of the high-voltage asymmetric NMOS. The channel region of the low-voltage PMOS, second dopants are injected to a third depth in the drain of the high-voltage PMOS and the channel region of the low-voltage NMOS, and the second and third depths are deeper than the first depth.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种减少工艺级数的半导体器件，并且在同一衬底上具有高电压和低压晶体管及其制造方法。解决方案：在CMOS集成电路中，其特征在于包括高压不对称NMOS，PMOS和低电压NMOS，PMOS由在衬底中具有第一深度的分离区隔开，第一掺杂剂注入到漏极中的第二深度高压不对称NMOS的区域。低压PMOS的沟道区域，第二掺杂剂被注入到高压PMOS的漏极和低压NMOS的沟道区的第三深度，第二和第三深度比第一深度。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2004104128A Sram device formed on soi substrate 有权
公开(公告)号：JP2004104128A
公开(公告)日：2004-04-02
申请号：JP2003311955
申请日：2003-09-03
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： GO SHOHO , KIM YOUNG-WUG
IPC分类号： H01L27/08 , G11C11/412 , H01L21/8238 , H01L21/8244 , H01L21/84 , H01L27/092 , H01L27/11 , H01L27/12 , H01L29/786
CPC分类号： H01L27/11 , H01L21/84 , H01L27/1104 , H01L27/1203 , Y10S257/903
摘要： PROBLEM TO BE SOLVED: To provide an SRAM device, which reduces the whole chip size, while enabling improvement in mobility and operating characteristics of a PMOS transistor.
SOLUTION: This SRAM device is formed on an SOI substrate comprising a first active region and a second active region. In each region, a first inverter, which consists of an NMOS transistor for a first access, an NMOS transistor for a first drive, and a PMOS transistor for a first load, and a second inverter, which consists of an NMOS transistor for a second access, an NMOS transistor for a second drive, and a PMOS transistor for a second load are formed. In the channels of the PMOS transistor for the first load and that for the second load, migration directions of the carriers are extended in the silicon crystal growth direction [110]. The drains of the NMOS transistors for accessing, those of the NMOS transistors for driving, and those of the PMOS transistor for loading are contacted in common.
COPYRIGHT: (C)2004,JPO

3. 发明专利

JP2004311999A Method of fabricating semiconductor element having shallow source/drain regions 审中-公开
标题翻译：制造具有深源/漏区的半导体元件的方法
公开(公告)号：JP2004311999A
公开(公告)日：2004-11-04
申请号：JP2004101507
申请日：2004-03-30
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： LEE SANG-JIN , KIN KEISHU , GO SHOHO , KANG HEE-SUNG
IPC分类号： H01L21/265 , H01L21/336 , H01L29/78 , H01L29/786
CPC分类号： H01L29/6653 , H01L21/2652 , H01L21/26586 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： PROBLEM TO BE SOLVED: To provide a method of fabricating a semiconductor element having shallow source/drain regions. SOLUTION: First spacers are formed on insulating layers on both sidewalls of each gate pattern. Deep source/drain regions are formed in the semiconductor substrate of interest so as to align with the first spacers. After removing the first spacers, the insulating layers are etched to form second spacers for offsetting on both of the sidewalls of each gate pattern. Shallow source/drain regions are formed in the regions of the semiconductor substrate aligned with the second spacers for offsetting and adjoining the deep source/drain regions. Thus, it is realized to form the deep source/drain regions prior to the shallow source/drain regions, and to control an overlap of the impurities ion-implanted into the shallow source/drain regions created through the gate pattern line width gradually reducing with the second spacer for offsetting. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种制造具有浅源/漏区的半导体元件的方法。解决方案：在每个栅极图案的两个侧壁上的绝缘层上形成第一间隔物。在感兴趣的半导体衬底中形成深源极/漏极区，以便与第一间隔物对准。在去除第一间隔物之后，蚀刻绝缘层以形成用于在每个栅极图案的两个侧壁上偏移的第二间隔物。在与第二间隔物对准的半导体衬底的区域中形成浅源极/漏极区，用于抵消和邻接深源极/漏极区。因此，实现了在浅源/漏区之前形成深源/漏区，并且控制离子注入到通过栅极图案线宽度产生的浅源/漏区中的杂质的重叠逐渐减小，用于抵消的第二间隔件。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2003318283A Semiconductor element using silicon germanium gate and method for manufacturing the same 有权
标题翻译：使用硅锗门的半导体元件及其制造方法
公开(公告)号：JP2003318283A
公开(公告)日：2003-11-07
申请号：JP2003080765
申请日：2003-03-24
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： RYU HYUK-JU , KIM YOUNG-WUG , GO SHOHO , KANG HEE-SUNG
IPC分类号： H01L21/28 , H01L21/306 , H01L21/3065 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49
CPC分类号： H01L27/092 , H01L21/823842
摘要： PROBLEM TO BE SOLVED: To provide a CMOS semiconductor element using a silicon germanium gate and a method for manufacturing it.
SOLUTION: A gate insulating film, a conductive electrode film with selective film quality, a silicon germanium electrode film and a conductive amorphous electrode film are successively formed on a semiconductor substrate so that a silicon germanium electrode film can be formed only in a PMOS area, and not formed in an NMOS area. Afterwards, the silicon germanium electrode film in the NMOS area is removed through a photo-etching process, and the silicon germanium electrode film is made to remain only in the PMOS area.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供使用硅锗栅的CMOS半导体元件及其制造方法。解决方案：在半导体衬底上依次形成栅极绝缘膜，具有选择性膜质量的导电电极膜，硅锗电极膜和导电非晶电极膜，从而可以仅形成硅锗电极膜 PMOS区域，并且不形成在NMOS区域中。之后，通过光蚀刻工艺去除NMOS区域中的硅锗电极膜，并使硅锗电极膜仅保留在PMOS区域中。版权所有（C）2004，JPO

5. 发明专利

JP2004266278A Mos transistor having raised source/drain structure, and manufacturing method of the same 有权
公开(公告)号：JP2004266278A
公开(公告)日：2004-09-24
申请号：JP2004055190
申请日：2004-02-27
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： GO SHOHO , KO YOUNG-GUN
IPC分类号： H01L21/28 , H01L21/336 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66628 , H01L29/665 , H01L29/66545 , H01L29/66621 , H01L29/7834
摘要： PROBLEM TO BE SOLVED: To provide a transistor which includes a source/drain diffusion region capable of easing or preventing the diffusion of impurities inside a channel region. SOLUTION: A gate electrode 314 is formed on a substrate for forming a gate 310. A gate insulating film 312 comprises a silicon oxide film (SiO2) and is formed on a bottom surface 314 and on the lower side surface of the gate electrode 314. An epitaxial film 305 comprises silicon or silicon germanium and is formed on the substrate adjacent to the facing surfaces of the gate 310. In the epitaxial film 305, a source diffusion region 306a and a drain diffusion region 306b are formed under a spacer 318. A source 308a and a drain 308b are formed on a part, where the source/drain diffusion regions 306a, 306b are exposed, that is, the prescribed part of the epitaxial region which is not located under the spacer. A MOS transistor comprises source/drain 308a, 308b raised alternatively and silicide regions 320a, 320b, and 320c for providing the gate electrode 314 with a low-resistance contact. COPYRIGHT: (C)2004,JPO&NCIPI

6. 发明专利

JP2001196472A STATIC RANDOM ACCESS MEMORY ELEMENT AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2001196472A
公开(公告)日：2001-07-19
申请号：JP2000380339
申请日：2000-12-14
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： GO SHOHO
IPC分类号： H01L21/8244 , H01L27/11 , H01L29/72
摘要： PROBLEM TO BE SOLVED: To provide a static random access memory element where the increase of the size of a cell that has been manufactured by proceeding with a process for manufacturing a standard CMOS logic without any additional masks and processes, and a method for manufacturing the memory element. SOLUTION: This static random access memory element is composed by one flip-flop circuit where two access transistors and inverters are in a pair, and connection lines 84 and 86 for interconnecting the input and output ends of the inverter, a word line 96, power lines 100, 104, and 108, and bit lines 102 and 106 are all formed by metal wiring, thus reducing wiring resistance, and proceeding with a process by a CMOS standard logic manufacturing process.

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