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1. 发明专利

JP2007300671A Image processing apparatus 有权
标题翻译：图像处理设备
公开(公告)号：JP2007300671A
公开(公告)日：2007-11-15
申请号：JP2007183403
申请日：2007-07-12
申请人： Ricoh Co Ltd , 株式会社リコー
发明人： OTSUKI TAKASHI , TSUKAGOSHI TOSHIHIRO
IPC分类号： H04N1/393 , G06T3/40 , H04N1/21
摘要： PROBLEM TO BE SOLVED: To provide an image processing apparatus which attains the magnifying/reducing processing of an image while suppressing a storage area from increasing. SOLUTION: The image processing apparatus for magnifying an image in which encoding data of the image composed of m×n pixels ((m), (n) is a natural number of ≥1) and encoded for every tile are decoded or an image to be encoded for every tile into s×t magnification ((s), (t) is a natural number of ≥1), is providedwith: a first storage device, which divides the decoded image or image to be encoded for each rectangular area that is the tile having a×b (0 COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种在抑制存储区域增加的同时实现图像的放大/缩小处理的图像处理装置。解决方案：用于对由m×n个像素（（m），（n）构成的图像的自然数≥1）的图像的编码数据进行放大的图像的图像处理装置被解码，要为每个瓦片编码为s×t放大率的图像（（s），（t）是≥1的自然数），提供：第一存储装置，其对于每个图像分割编码的图像或图像，矩形区域，其是具有×b（0

2. 发明专利

JP2007087082A Information processor and option device sharing method 审中-公开
标题翻译：信息处理器和选项设备共享方法
公开(公告)号：JP2007087082A
公开(公告)日：2007-04-05
申请号：JP2005274608
申请日：2005-09-21
申请人： Ricoh Co Ltd , 株式会社リコー
发明人： IKEDA JUNICHI , OSHIKIRI KOJI , TERAO NORIYUKI , OIZUMI MITSUHIRO , YONEDA YUTAKA , NUMAKURA SATORU , KITAGAWA HIROO , TANAKA TOMONORI , KANEHARA HIROYUKI , TANAKA HIDETAKE , HAMAGUCHI ITSUKI , IWASAKI KEIICHI , TSUKAGOSHI TOSHIHIRO , TSUMURA NAOKI
IPC分类号： G06F13/14 , B41J29/38 , G06F13/36 , G06F13/38 , H04N1/00
摘要： PROBLEM TO BE SOLVED: To provide an information processor capable of executing a processing necessitating an option device, which is not mounted on the processor, without adding the option device. SOLUTION: The information processor 1(A) retrieves an option device for information processing mounted on the other information processor 1(B, C, D) on a network 20 through a network 20, and issues the use request of the option device to the other desired information processor, and receives the use right of the option device from the other information processor 1(B, C, D) as the issue destination of the use request of the option device, and executes information processing by using the option device of the other information processor 1(B, C, D) whose right to use has been received. Thus, it is possible to execute processing requiring an option device which is not mounted on the information processor 1(A) without adding any option device. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种信息处理器，其能够执行不需要添加选项设备而不需要安装在处理器上的选项设备的处理。解决方案：信息处理器1（A）通过网络20检索在网络20上安装在其他信息处理器1（B，C，D）上的信息处理选项设备，并且发出选项的使用请求设备到另一个期望的信息处理器，并且从其他信息处理器1（B，C，D）接收到选项设备的使用权作为选项设备的使用请求的发行目的地，并且通过使用已经接收到使用权的其他信息处理器1（B，C，D）的选项设备。因此，可以在不添加任何选项装置的情况下执行需要未安装在信息处理器1（A）上的选项装置的处理。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2007193454A Unit including storage device having two or more memory areas and memory control system 有权
标题翻译：包含具有两个或多个记忆区域和存储器控制系统的存储设备的单元
公开(公告)号：JP2007193454A
公开(公告)日：2007-08-02
申请号：JP2006009258
申请日：2006-01-17
申请人： Ricoh Co Ltd , 株式会社リコー
发明人： IWASAKI KEIICHI , IKEDA JUNICHI , OSHIKIRI KOJI , KITAGAWA HIROO , TANAKA TOMONORI , KANEHARA HIROYUKI , TANAKA HIDETAKE , HAMAGUCHI ITSUKI , TSUKAGOSHI TOSHIHIRO , TSUMURA NAOKI
IPC分类号： G06F3/12 , B41J29/38
摘要： PROBLEM TO BE SOLVED: To provide a unit and a memory control system, capable of performing high-speed data transfer even in transferring a large capacity of data. SOLUTION: In a unit 31 connected with the other unit 32, a storage device 311 has a bus master 313 and a bus slave 314 corresponding to memory areas 315 and 316. The bus master 313 includes a data writing monitoring means for monitoring writing of data to the memory area 315 corresponding to the bus master 313, a data transfer request means for requesting, upon detection of writing of data to the memory area 315 by the data writing monitoring means, transfer of data to the unit 32, and a data transmission means transmitting data to the unit 32. The bus slave 314 includes a data receiving means receiving data transferred from the unit 32 according to a data transfer request from the unit 32 and storing the data in the memory area corresponding to the bus slave 314. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种单元和存储器控制系统，即使在传送大容量数据时也能够进行高速数据传送。解决方案：在与另一单元32连接的单元31中，存储装置311具有对应于存储区域315和316的总线主站313和总线从站314。总线主站313包括用于监视的数据写入监视装置将数据写入对应于总线主机313的存储区域315，数据传送请求装置，用于在通过数据写入监视装置检测到向存储区域315写入数据时请求数据传送到单元32，以及数据发送装置向单元32发送数据。总线从设备314包括数据接收装置，根据来自单元32的数据传送请求接收从单元32传送的数据，并将数据存储在与总线从站对应的存储区域中 314.版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2007272871A Information processing apparatus and data communication method 审中-公开
标题翻译：信息处理设备和数据通信方法
公开(公告)号：JP2007272871A
公开(公告)日：2007-10-18
申请号：JP2007014281
申请日：2007-01-24
申请人： Ricoh Co Ltd , 株式会社リコー
发明人： OSHIKIRI KOJI , TERAO NORIYUKI , IKEDA JUNICHI , OIZUMI MITSUHIRO , NUMAKURA SATORU , YONEDA YUTAKA , TANAKA TOMONORI , KANEHARA HIROYUKI , IWASAKI KEIICHI , TSUKAGOSHI TOSHIHIRO , HAMAGUCHI ITSUKI , TANAKA HIDETAKE , TSUMURA NAOKI , KITAGAWA HIROO
IPC分类号： G06F13/14 , G06F13/38
摘要： PROBLEM TO BE SOLVED: To provide an information processing apparatus and a data communication method for freely expanding devices having various traffics of different characteristics with respect to a high-speed serial switch fabric.
SOLUTION: The information processing apparatus 1 includes a plurality of devices 3-12 connected thereto through the high-speed serial switch fabric 2 capable of mapping a traffic class that can differentiate traffics onto a virtual channel. In data communication between the devices 3-12, the traffic class is set for each group according to a group table in which the data communication is classified into groups based on properties of a traffic between the devices 3-12, and each of the set traffic classes is assigned to different virtual channels and given a priority of data communication. This allows for freely expanding of the devices 3-12 having various traffics of different characteristics with respect to the high-speed serial switch fabric 2.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种信息处理装置和数据通信方法，用于自由扩展具有相对于高速串行交换结构的不同特征的各种业务的设备。解决方案：信息处理设备1包括通过高速串行交换矩阵2连接到其上的多个设备3-12，能够映射可以将业务区分到虚拟信道上的业务等级。在设备3-12之间的数据通信中，根据组中的每个组设置业务类别，根据组表，其中数据通信根据设备3-12之间的业务的属性被分类成组，并且每个组业务类被分配给不同的虚拟通道，并给出数据通信的优先级。这允许相对于高速串行交换结构2自由扩展具有不同特征的各种业务的设备3-12。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2005227843A System and method for designing semiconductor device 审中-公开
标题翻译：用于设计半导体器件的系统和方法
公开(公告)号：JP2005227843A
公开(公告)日：2005-08-25
申请号：JP2004033366
申请日：2004-02-10
申请人： Ricoh Co Ltd , 株式会社リコー
发明人： TSUKAGOSHI TOSHIHIRO
IPC分类号： G06F17/50
摘要： PROBLEM TO BE SOLVED: To efficiently increase fault detection rate without causing a large increase in gates.
SOLUTION: A module with a low fault detection rate is determined (step 206) through previously run fault simulations (step 201-205) and its information is fed back to process and correct a corresponding RTL description in such a way as to easily increase its fault detection rate (step 207, 210, 211). A list of remaining faults resulting from the fault simulations is fed back (step 207, 210) and a logic circuit on a gate level is corrected (step 211) in such a way as to divide the number of steps of combinational circuits after logic synthesis so as to easily increase the fault detection rate after the logic synthesis (step 208-212).
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：有效提高故障检测率，而不会导致门的大幅增加。解决方案：通过先前运行的故障模拟（步骤201-205）确定具有低故障检测速率的模块（步骤206），并且将其信息反馈到处理和校正相应的RTL描述，使得容易地增加其故障检测率（步骤207,210,211）。反馈由故障模拟产生的剩余故障的列表（步骤207,210），并且校正门级上的逻辑电路（步骤211），以便在逻辑合成之后划分组合电路的步数以便在逻辑合成之后容易地增加故障检测率（步骤208-212）。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2011062021A Dead time generating circuit and motor control device 有权
标题翻译：死机时间发生电路和电机控制装置
公开(公告)号：JP2011062021A
公开(公告)日：2011-03-24
申请号：JP2009210673
申请日：2009-09-11
申请人： Ricoh Co Ltd , 株式会社リコー
发明人： UEDA YASUO , TOKUDA MASASHI , TSUKAGOSHI TOSHIHIRO
IPC分类号： H02M7/48 , H03K17/28 , H03K17/687
CPC分类号： H02M1/38 , H03K5/1515 , H03K17/16
摘要： PROBLEM TO BE SOLVED: To reliably generate dead time even if a control signal has a pulse shorter than a discharge time of a capacitor. SOLUTION: A predetermined current I2 is generated in accordance with an external resistor R1, and based on a dead time control signal S3 and a predetermined comparator signal S2, only a predetermined delay time t3 is delayed from the rising and falling of the dead time control signal S3 to form a dead time generation signal S4. Based on the dead time generation signal S4, charging or discharging of a capacitor C1 is controlled using the current I2. When a voltage Vc of the capacitor C1 is compared with a predetermined threshold voltage Vth, and the voltage Vc exceeds the threshold voltage Vth, the dead time is generated by generating the comparator signal S2 and stopping the dead time generation signal S4. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：即使控制信号具有比电容器的放电时间短的脉冲，也可靠地产生死区时间。
解决方案：根据外部电阻器R1产生预定电流I2，并且基于死区时间控制信号S3和预定比较器信号S2，只有预定的延迟时间t3从...的上升和下降延迟死区时间控制信号S3以形成死区时间产生信号S4。基于死区产生信号S4，使用电流I2控制电容器C1的充电或放电。当将电容器C1的电压Vc与预定阈值电压Vth进行比较，并且电压Vc超过阈值电压Vth时，通过产生比较器信号S2并停止死区时间产生信号S4来产生死区时间。版权所有（C）2011，JPO＆INPIT

7. 发明专利

JP2005322694A Method for designing layout of semiconductor integrated circuit and its fabrication process 审中-公开
标题翻译：半导体集成电路布局及其制造工艺的设计方法
公开(公告)号：JP2005322694A
公开(公告)日：2005-11-17
申请号：JP2004137723
申请日：2004-05-06
申请人： Ricoh Co Ltd , 株式会社リコー
发明人： KUMANO YOSHINORI , TSUKAGOSHI TOSHIHIRO
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide a method for designing layout in which required number of flip-flop cells for circuit correction can be secured regardless of the number of clock systems and without deteriorating clock skew of existing flip-flop cells and dummy flip-flop cells by suppressing increase in the number of gates due to addition of dummy cells as much as possible.
SOLUTION: In the image drawing, the semiconductor integrated circuit comprises clock systems CTS1, CTS2 and CTS3, cells 4, 8 and 11 connected with respective output lines 5, existing FFs 6, 9 and 12, and dummy cells 7, 10 and 13 connected with respective output lines 5.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于设计布局的方法，其中可以确保用于电路校正的所需数量的触发器单元，而不管时钟系统的数量如何，并且不会使现有触发器单元和虚拟器件的时钟偏移恶化通过尽可能地抑制由于增加虚拟单元而导致的门数量的增加，触发器单元。解决方案：在图像绘制中，半导体集成电路包括时钟系统CTS1，CTS2和CTS3，与相应输出线5，现有FF 6,9和12连接的单元4,8和11，以及虚设单元7,10 和13与各输出线5相连。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2004259879A Regulator built-in semiconductor device 有权
标题翻译：调节器内置半导体器件
公开(公告)号：JP2004259879A
公开(公告)日：2004-09-16
申请号：JP2003047844
申请日：2003-02-25
申请人： Ricoh Co Ltd , 株式会社リコー
发明人： TSUKAGOSHI TOSHIHIRO
IPC分类号： H01L27/04 , G05F1/56 , H01L21/822
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device eliminating concerns in which a power consumption is increased and disadvantages such as the generation of power-supply noises to an adjacent logic region, the drop of an internal power-supply voltage due to a (large) current consumption or the like are caused as the effects of the increase in the large-scale semiconductor device having a high integration.
SOLUTION: In the semiconductor device in which the internal power-supply voltage for internal logic-circuit regions and an external power-supply voltage for an external input/output region differ, and which has built-in regulators supplying the internal logic-circuit regions with a power supply by stepping down a single external power supply; the semiconductor device has a plurality of the regulators capable of discretely setting generated voltages, and has a function in which the internal logic-circuit regions divided into two or more are supplied with different voltages.
COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种消除电力消耗增加的问题的半导体器件以及诸如向相邻逻辑区域产生电源噪声的缺点，由于内部电源电压的下降，由于引起大的电流消耗等作为具有高集成度的大型半导体器件的增加的效果。解决方案：在内部逻辑电路区域的内部电源电压和外部输入/输出区域的外部电源电压不同的半导体器件中，内置稳压器提供内部逻辑通过降低单个外部电源的电源供电; 半导体器件具有能够离散地设置所产生的电压的多个稳压器，并且具有其中被分成两个或更多个的内部逻辑电路区域被提供不同电压的功能。版权所有（C）2004，JPO＆NCIPI

9. 发明专利

JP2007129306A Pll control circuit 审中-公开
标题翻译： PLL控制电路
公开(公告)号：JP2007129306A
公开(公告)日：2007-05-24
申请号：JP2005318169
申请日：2005-11-01
申请人： Nec Corp , Nec Saitama Ltd , Ricoh Co Ltd , 埼玉日本電気株式会社 , 日本電気株式会社 , 株式会社リコー
发明人： OTSUKI MICHIHITO , SUKEGAWA MASAZUMI , IWASAKI MITSUTAKA , TSUKAGOSHI TOSHIHIRO
IPC分类号： H03L7/14
CPC分类号： H03L7/183 , H03L7/14
摘要： PROBLEM TO BE SOLVED: To provide a PLL circuit which prevents loss of data or sequence processing even if a reference clock fluctuates during PLL operation. SOLUTION: The PLL control circuit which outputs a PLL clock in response to the reference clock is provided with a frequency adjusting circuit 45 for performing frequency adjustment so that the frequency of the PLL is substantially constant, even when the reference clock fluctuates. The frequency adjusting circuit 45 changes a set value of a counter for deciding the frequency of the PLL clock in accordance with the change of the reference clock frequency. COPYRIGHT: (C)2007,JPO&INPIT

10. 发明专利

JP2007087083A Information processor and storage device sharing method 有权
标题翻译：信息处理器和存储设备共享方法
公开(公告)号：JP2007087083A
公开(公告)日：2007-04-05
申请号：JP2005274609
申请日：2005-09-21
申请人： Ricoh Co Ltd , 株式会社リコー
发明人： IKEDA JUNICHI , TANAKA TOMONORI , KANEHARA HIROYUKI , IWASAKI KEIICHI , TSUKAGOSHI TOSHIHIRO , HAMAGUCHI ITSUKI , TANAKA HIDETAKE , KITAGAWA HIROO , TSUMURA NAOKI , TERAO NORIYUKI , OIZUMI MITSUHIRO , YONEDA YUTAKA , NUMAKURA SATORU , OSHIKIRI KOJI
IPC分类号： G06F13/10 , G06F12/00
摘要： PROBLEM TO BE SOLVED: To provide an information processor capable of executing processing necessitating a region exceeding the capacity of a storage device mounted on the processor without increasing the storage device capacity per unit. SOLUTION: The information processor 1(A) retrieves the free capacity of storage devices 8 and 9 mounted on the other information processor 1(B, C, D) on a network 20 for storing data through a network 20, and issues the use request of the storage devices 8 and 9 to the other desired information processor 1(B, C, D), and receives the use right of the free regions of the storage devices 8 and 9 from the other information processor 1(B, C, D) as the issue destination of the use right of the storage devices 8 and 9, and executes information processing by using the free regions of the storage devices 8 and 9 of the other information processor 1(B, C, D) whose right use has been received. Thus, it is possible to execute processing requiring a region exceeding the capacity of the storage device mounted on an information processor without increasing the storage device capacity per unit. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供能够执行处理的信息处理器，其需要超过安装在处理器上的存储装置的容量的区域，而不增加每单位的存储装置容量。解决方案：信息处理器1（A）检索在网络20上安装在另一信息处理器1（B，C，D）上的存储设备8和9的可用容量，用于通过网络20存储数据，并且发出存储装置8和9对另一个所需信息处理器1（B，C，D）的使用请求，并且从其他信息处理器1（B，C，D）接收存储装置8和9的空闲区域的使用权， C，D）作为存储装置8和9的使用权的发行目的地，并且通过使用其他信息处理器1（B，C，D）的存储装置8和9的空闲区域执行信息处理（B，C，D）已收到正确使用。因此，可以执行需要超过安装在信息处理器上的存储装置的容量的区域的处理，而不增加每单位的存储装置容量。版权所有（C）2007，JPO＆INPIT

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