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1. 发明专利

JP2006166469A Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路设备
公开(公告)号：JP2006166469A
公开(公告)日：2006-06-22
申请号：JP2005364895
申请日：2005-12-19
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： MIZUNO HIROYUKI , MIYAZAKI SUKEYUKI , ISHIBASHI KOICHIRO
IPC分类号： H03K19/096 , G06F1/04 , G06F1/08 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which has improved power consumption, packaging density, stability and stable time. SOLUTION: The semiconductor integrated circuit device is equipped with a logic circuit including MIS transistors formed on a semiconductor substrate, wherein substrate bias control circuit is provided for balancing a first substrate bias voltage Vbp0, which is applied to a first conductive MIS transistor, and a second substrate bias voltage Vbn0, which is applied to a second conductive MIS transistor. The substrate bias control circuit includes first and second control circuits for controlling the threshold voltages of MIS transistors constituting the logic circuit, and an oscillation circuit that includes the MIS transistors formed on the semiconductor substrate, and is configured to vary the frequency of the oscillation output. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有改善的功耗，封装密度，稳定性和稳定时间的半导体集成电路器件。解决方案：半导体集成电路器件配备有形成在半导体衬底上的MIS晶体管的逻辑电路，其中提供衬底偏置控制电路，用于平衡施加到第一导电MIS晶体管的第一衬底偏置电压Vbp0 以及施加到第二导电MIS晶体管的第二衬底偏置电压Vbn0。衬底偏置控制电路包括用于控制构成逻辑电路的MIS晶体管的阈值电压的第一和第二控制电路，以及包括形成在半导体衬底上的MIS晶体管的振荡电路，并且被配置为改变振荡输出的频率。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2005354718A Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路设备
公开(公告)号：JP2005354718A
公开(公告)日：2005-12-22
申请号：JP2005187224
申请日：2005-06-27
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： MIYAZAKI SUKEYUKI , ISHIBASHI KOICHIRO
IPC分类号： H01L27/04 , G11C11/407 , H01L21/822 , H01L21/8234 , H01L27/088 , H03K19/00 , H03K19/003 , H03K19/094 , H03K19/0948 , H03K19/096
CPC分类号： H03K19/00384
摘要： PROBLEM TO BE SOLVED: To make acceleration of an operating speed of a CMOS circuit compatible with reduction of power consumption.
SOLUTION: A semiconductor integrated circuit device to which power is supplied from a battery, includes a main circuit (LSI), a clock frequency control circuit (FRQCNT) for controlling a frequency of a clock signal supplied to the main circuit, a power supply voltage control circuit (VDDCNT) for controlling a power supply voltage supplied to the main circuit, and a substrate bias control circuit (VBBCNT) for controlling a substrate bias in the main circuit. All of a frequency of the clock signal, a voltage value of the power supply voltage and a voltage value of the substrate bias are controlled in accordance with an operational performance required for the main circuit, and at least any one of the frequency of the clock signal, the voltage value of the power supply voltage and the voltage value of the substrate bias is controlled according to the remaining power of the battery, so that variations of circuit characteristics are suppressed.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：使CMOS电路的工作速度的加速兼容于功耗的降低。解决方案：从电池供电的半导体集成电路器件包括主电路（LSI），用于控制提供给主电路的时钟信号的频率的时钟频率控制电路（FRQCNT），用于控制提供给主电路的电源电压的电源电压控制电路（VDDCNT）以及用于控制主电路中的衬底偏置的衬底偏置控制电路（VBBCNT）。根据主电路所需的操作性能来控制时钟信号的频率，电源电压的电压值和衬底偏置的电压值，并且时钟的频率中的至少一个信号，根据电池的剩余功率来控制电源电压的电压值和基板偏压的电压值，从而抑制电路特性的变化。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2004024551A Semiconductor device for sensor system 审中-公开
公开(公告)号：JP2004024551A
公开(公告)日：2004-01-29
申请号：JP2002185450
申请日：2002-06-26
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： YAMASHITA SHUNZO , SUZUKI TAKASHI , ARITSUKA TOSHIYUKI , MIYAZAKI SUKEYUKI , NAKANO SADASHIGE
IPC分类号： G01P15/125 , A61B5/00 , A61B5/01 , A61B5/0205 , A61B5/024 , A61B5/0245 , A61B5/053 , A61B5/11 , A61B5/145 , A61B5/1455 , G01D9/00 , G01K7/01 , G01N33/483 , G01N33/50 , G08C15/00 , G08C17/00 , H01L23/34 , H01L35/32
CPC分类号： A61B5/0002 , A61B5/02055 , A61B5/02427 , A61B5/0531 , A61B5/11 , A61B5/7232 , A61B2560/0209 , A61B2560/0412 , A61B2562/0219 , A61B2562/028 , A61B2562/08 , G01D9/005 , G01K7/01 , G01K2215/00 , G01P15/125 , G01P2015/0814 , H01L35/32 , H01L2924/0002 , Y10S128/903 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide s semiconductor device for sensor system which has reduced weight, size and dispenses with replacing of a battery. SOLUTION: A sensor chip (SCHIP1) is provided with sensors (TD1, AS1, PD1 and GS1), an A/D conversion circuit (AD1), a microprocessor (CPU1), a memory (MEM1), a transmission circuit (RF1) and a power generator (CM1). The sensors, the A/D conversion circuit, the microprocessor, the memory and the transmission circuit are formed on one of substrate faces (SIDE1) and the power generator is formed on a substrate face (SIDE2) opposite to the substrate surface. COPYRIGHT: (C)2004,JPO

4. 发明专利

JP2008072406A A/d converter and receiver using the same 有权
标题翻译： A / D转换器和接收器使用它
公开(公告)号：JP2008072406A
公开(公告)日：2008-03-27
申请号：JP2006248800
申请日：2006-09-14
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： NAKAGAWA SHIGEO , MIYAZAKI SUKEYUKI , ONO TAKEKAZU
IPC分类号： H03M1/36
摘要： PROBLEM TO BE SOLVED: To make a sample/hold circuit and a comparator constituting an A/D converter low power consumption. SOLUTION: In the sample/hold circuit SHC of a first stage, connection nodes of two capacitors C2 and C3 are connected to an operation potential which is substantially stably maintained through a switch SW8 during a sample mode. During the sample mode, it is possible to accurately sample an analog input signal Vin to the capacitor C2 and input offset voltage of an operational amplifier OPA to the capacitor C3 so that low power consumption and high performance can be achieved during the sample mode. By control by a bias control circuit BCC, a preamplifier AMP of a comparator COP of the post stage performs amplification with a large amplification rate when differential voltage of differential input signals Vsig and Vref supplied from outputs of the sample/hold circuit SHC of the first stage is small, and performs amplification at a small amplification rate when the differential voltage is sufficiently large. The acceleration and low power consumption of the comparator COP of the post stage can be achieved. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：使构成A / D转换器的采样/保持电路和比较器的功耗较低。解决方案：在第一级的采样/保持电路SHC中，两个电容器C2和C3的连接节点连接到在采样模式期间通过开关SW8基本上稳定地保持的操作电位。在采样模式下，可以将模拟输入信号Vin精确地采样到电容器C2，并将运算放大器OPA的失调电压输入到电容器C3，以便在采样模式期间可以实现低功耗和高性能。通过偏置控制电路BCC的控制，后级的比较器COP的前置放大器AMP在从第一级的采样/保持电路SHC的输出提供的差分输入信号Vsig和Vref的差分电压的时候以大的放大率进行放大并且当差分电压足够大时以小的放大率进行放大。可以实现后级比较器COP的加速和低功耗。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2004282776A Semiconductor integrated circuit device 有权
公开(公告)号：JP2004282776A
公开(公告)日：2004-10-07
申请号：JP2004129490
申请日：2004-04-26
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： MIZUNO HIROYUKI , MIYAZAKI SUKEYUKI , ISHIBASHI KOICHIRO
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L27/088 , H03K19/094 , H03K19/096
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which is improved in power consumption, packaging density, stability, stable time and the like.
SOLUTION: In the semiconductor integrated circuit device equipped with a logic circuit including MIS (metal insulator semiconductor) transistors formed on a semiconductor substrate, a substrate bias control circuit is provided for balancing a first substrate bias voltage Vbp0 which is applied to a first conductive MIS transistor, and a second substrate bias voltage Vbn0 which is applied to a second conductive MIS transistor. The substrate bias control circuit includes first and second control circuits for controlling threshold voltages of MIS transistors comprising the logic circuit, and an oscillation circuit that includes the MIS transistors formed on the semiconductor substrate, and is configured to vary a frequency of an oscillated output.
COPYRIGHT: (C)2005,JPO&NCIPI

6. 发明专利

JP2004228417A Semiconductor integrated circuit apparatus 有权
公开(公告)号：JP2004228417A
公开(公告)日：2004-08-12
申请号：JP2003016040
申请日：2003-01-24
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： MIYAZAKI SUKEYUKI , KAWAHARA TAKAYUKI
IPC分类号： H01L27/04 , H01L21/822 , H03K19/0948
摘要： PROBLEM TO BE SOLVED: To provide a high-frequency low-power circuit technique which achieves with low consuming powers the necessary performances for respective circuit modules, and deals with the contractions of their design terms and testing times and the variations of their manufacturing processes, in an integrated circuit apparatus formed out of a plurality of CMOS circuit modules. SOLUTION: In a CMOS circuit chip forming the semiconductor integrated circuit apparatus, a performance measuring circuit PMC is provided, and there are provided at every circuit function module CFM present in the CMOS circuit chip, a storage-table circuit MTC, a clock-frequency controlling circuit CFC, a power-supply-voltage controlling circuit SVC, and a board-bias controlling circuit BBC. When testing the chip, the performance measuring circuit so measures such performances of the circuit function module as its operational speed and consuming power as to store the performance data in the corresponding storage-table circuit, and the storage-table circuit so measures the data amount fed to the circuit function module as to select its optimal clock frequency, power-supply voltage, and board bias. COPYRIGHT: (C)2004,JPO&NCIPI

7. 发明专利

JP2009033688A Semiconductor integrated circuit and operating method for ultra wideband-impulse radio transmitter 审中-公开
标题翻译：半导体集成电路和超宽带无线电发射机的操作方法
公开(公告)号：JP2009033688A
公开(公告)日：2009-02-12
申请号：JP2007198252
申请日：2007-07-31
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： NORIMATSU SUUTAI , MIYAZAKI SUKEYUKI
IPC分类号： H04B1/04 , H04B1/717 , H04J13/00 , H04L25/49
CPC分类号： H04L25/03834 , H04B1/71635 , H04B1/7174 , H04L25/06
摘要： PROBLEM TO BE SOLVED: To provide an ultra wideband-impulse radio transmitter which can achieve characteristics that conform to predetermined rules with high manufacturing yields or high stability, when the transmitter is realized in a semiconductor integrated circuit. SOLUTION: In the semiconductor integrated circuit, a transmitted pulse, having an impulse waveform is generated by a pull-up current I PU and a pull-down current I PD of a charge pump ChPump1... in pattern-generating cells of a pattern generator. In a first calibration operation of the semiconductor integrated circuit, variations in the amplitude of the transmitted pulse are detected. At least one of the pull-up current and the pull-down current of the charge pump is controlled by a first calibration control signal CAL_I PU that corresponds to an amplitude detection result. In a second calibration operation, fluctuations in DC level are detected as well, immediately after the repeated pulse of the transmitted pulse is generated. By means of a second calibration control signal CAL_I PD that corresponds to a DC detection result, imbalance between the pull-up current and the pull-down current of the charge pump is reduced. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种超宽带脉冲无线电发射机，当发射机在半导体集成电路中实现时，可以实现符合具有高制造产量或高稳定性的预定规则的特性。解决方案：在半导体集成电路中，具有脉冲波形的发送脉冲通过上拉电流I PU 和下拉电流I SB SB >电荷泵ChPump1 ...在图案发生器的图案生成单元中。在半导体集成电路的第一校准操作中，检测发射脉冲幅度的变化。电荷泵的上拉电流和下拉电流中的至少一个由对应于振幅检测结果的第一校准控制信号CAL_I PU 控制。在第二校准操作中，在发送脉冲的重复脉冲之后立即检测DC电平的波动。通过对应于直流检测结果的第二校准控制信号CAL_I PD ，减小了电荷泵的上拉电流和下拉电流之间的不平衡。版权所有（C）2009，JPO＆INPIT

8. 发明专利

JP2008199673A Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：JP2008199673A
公开(公告)日：2008-08-28
申请号：JP2008120989
申请日：2008-05-07
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： MIZUNO HIROYUKI , MIYAZAKI SUKEYUKI , ISHIBASHI KOICHIRO
IPC分类号： H03K19/094 , H01L21/822 , H01L27/04 , H03K17/00 , H03K17/693 , H03K19/0175 , H03K19/096
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which enhances power consumption, mounting density, stability, stable time, etc. SOLUTION: A semiconductor integrated circuit device comprises: a first circuit block including a first MIS transistor of a first conductive type and a second MIS transistor of a second conductive type; a first substrate control block including a first switch circuit for supplying a substrate power source to the first MIS transistor; a second circuit block including a third MIS transistor of the first conductive type and a fourth MIS transistor of the second conductive type; a second substrate control block including a second switch circuit for supplying a substrate power source to the third MIS transistor; a substrate bias control circuit for supplying substrate power sources to the first and the third MIS transistors; and a control circuit for controlling the first and the second switch circuits, wherein the first switch circuit and the second switch circuit are controlled independently by the control circuit. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决方案：提供一种提高功耗，安装密度，稳定性，稳定时间等的半导体集成电路器件。解决方案：半导体集成电路器件包括：第一电路块，包括第一MIS 第一导电类型的晶体管和第二导电类型的第二MIS晶体管; 第一衬底控制块，包括用于向第一MIS晶体管提供衬底电源的第一开关电路; 第二电路块，包括第一导电类型的第三MIS晶体管和第二导电类型的第四MIS晶体管; 第二基板控制块，包括用于向第三MIS晶体管提供基板电源的第二开关电路; 用于向第一和第三MIS晶体管提供衬底电源的衬底偏置控制电路; 以及用于控制第一和第二开关电路的控制电路，其中第一开关电路和第二开关电路由控制电路独立控制。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2007142790A Receiver, communication device, and controller using it 有权
标题翻译：接收器，通信设备和使用它的控制器
公开(公告)号：JP2007142790A
公开(公告)日：2007-06-07
申请号：JP2005333670
申请日：2005-11-18
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： FUJIWARA RYOSUKE , NAKAGAWA SHIGEO , MIYAZAKI SUKEYUKI
IPC分类号： H04B1/7183 , H04J13/00 , H04L7/10
CPC分类号： H04L7/0058 , H04B1/7183 , H04L7/10
摘要： PROBLEM TO BE SOLVED: To perform initial synchronization capturing of an ultra wideband signal at high speed and with high precision without increasing complexity of hardware and consumption power.
SOLUTION: The communication device exchanges information by an intermittent pulse train signal. In a process which carries out an initial synchronization capturing of incoming pulses; all phases between pulses are searched by predetermined search resolution, a region is estimated where there is the highest peak phase of an output value, in the next step, search of all phases in the estimated region is repeated, regions where there are peak phases is narrowed in a predetermined range, and the synchronization capturing is performed in detail in the estimated regions. In the respective steps, a threshold value which discriminates whether there is a signal or not, or a gain on an analog unit are controlled for respective steps. Moreover, the search resolution is made large at a time of estimation of the peak phase, and fine at a time of detail synchronization capturing.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：以高速和高精度执行超宽带信号的初始同步捕获，而不增加硬件和消耗功率的复杂性。解决方案：通信设备通过间歇脉冲串信号来交换信息。在进行进入脉冲的初始同步捕获的过程中; 通过预定的搜索分辨率搜索脉冲之间的所有相位，在下一步骤中估计出具有最高峰值相位的区域，在重新估计估计区域中的所有相位的搜索，存在峰值相位的区域是在预定范围内变窄，并且在估计区域中详细地执行同步捕获。在各个步骤中，对于各个步骤控制判别是否存在信号的阈值或模拟单元的增益。此外，在估计峰值相位时，搜索分辨率变大，并且在详细同步捕获时精细。版权所有（C）2007，JPO＆INPIT

10. 发明专利

JP2007060722A Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路设备
公开(公告)号：JP2007060722A
公开(公告)日：2007-03-08
申请号：JP2006316669
申请日：2006-11-24
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： MIYAZAKI SUKEYUKI , ISHIBASHI KOICHIRO , ONO TAKEKAZU
IPC分类号： H03K19/094 , H01L21/822 , H01L27/04 , H03K19/096
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device with an increasing speed while assuring the improvement of yield of products and reliability. SOLUTION: The semiconductor integrated circuit device having a main circuit comprising MOSFET and a substrate bias circuit for supplying positive bias voltage to a semiconductor region in which the MOSFET is formed, is provided with a current limiting circuit for limiting current being supplied to the semiconductor region in response to a substrate current flowing between the semiconductor region where the MOSFET is formed and the source. COPYRIGHT: (C)2007,JPO&INPIT

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