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1. 发明专利

JP2009118049A Discrete time amplifier circuit and analog-digital converter 审中-公开
标题翻译：离散时间放大器电路和模拟数字转换器
公开(公告)号：JP2009118049A
公开(公告)日：2009-05-28
申请号：JP2007287217
申请日：2007-11-05
申请人： Panasonic Corp , パナソニック株式会社
发明人： AKIZUKI TAIJI , ADACHI HISASHI , MAEDA CHIKO
IPC分类号： H03F3/45 , H03M1/12
CPC分类号： H03F3/45475 , H03F3/45183 , H03F3/45946 , H03F2200/411 , H03F2203/45136 , H03F2203/45166 , H03F2203/45421 , H03F2203/45424 , H03F2203/45512 , H03F2203/45551 , H03F2203/45634 , H03M1/1245
摘要： PROBLEM TO BE SOLVED: To attain simplified circuit and low current consumption in a discrete time amplifier circuit and an AD converter, to improve convergence from a transient response state to a steady state of the amplifier circuit and to reduce noise and distortion owing to variation in output common-mode voltage. SOLUTION: The discrete time amplifier circuit and the AD converter are provided with a switched-capacitor common-mode feedback (CMFB) circuit 2 capable of detecting and feeding back the output common-mode voltage at every sampling in the case that the circuit operates at double sampling timing (the circuit operates by every half period). COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了在离散时间放大器电路和AD转换器中实现简化的电路和低电流消耗，以改善从瞬态响应状态到放大器电路的稳定状态的收敛，并且减少由于输出共模电压的变化。解决方案：离散时间放大器电路和AD转换器设置有开关电容共模反馈（CMFB）电路2，其能够在每次采样时检测并反馈输出共模电压，电路工作在双采样定时（电路每半个周期运行）。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2012191436A Received signal processing device 有权
标题翻译：接收信号处理装置
公开(公告)号：JP2012191436A
公开(公告)日：2012-10-04
申请号：JP2011053202
申请日：2011-03-10
申请人： Panasonic Corp , パナソニック株式会社
发明人： KOBAYASHI MASASHI , FUJITA TAKU , AKIZUKI TAIJI
IPC分类号： H03F3/34 , H03G3/20 , H04B1/30
CPC分类号： H04L25/06 , H03F1/0277 , H03F3/189 , H03F3/45183 , H03F3/45748 , H03F3/72 , H03F2200/294 , H03F2200/336 , H03F2200/405 , H03F2200/411 , H03F2200/507 , H03F2203/45212 , H03F2203/45352 , H03F2203/45702 , H03F2203/7215 , H03F2203/7221 , H03F2203/7227 , H03F2203/7231 , H03F2203/7236 , H03G3/3068 , H04B1/30
摘要： PROBLEM TO BE SOLVED: To provide a received signal processing device that has a small circuit scale and a low power consumption.SOLUTION: The received signal processing device includes: a mixer section for combining a local oscillation signal with a high frequency received signal to effect frequency conversion; an amplification section including a plurality of variable gain amplifiers in a multistage configuration; a conversion section for converting an analog signal amplified by the amplification section to a digital signal; a switch disposed at the back of each variable gain amplifier; a bypass switch section for setting open/closed a path along which an output of one variable gain amplifier bypasses the later variable gain amplifiers to enter the conversion section; a switch control section for controlling the switch and the bypass switch section such that the output of each variable gain amplifier bypasses the later variable gain amplifiers to enter the conversion section; and a DC offset control section for setting a DC offset compensation value in accordance with a gain set in a variable gain amplifier to be corrected when the received signal bypasses the variable gain amplifier to be corrected and the output of the variable gain amplifier to be corrected bypasses the later variable gain amplifiers to enter the conversion section.
摘要翻译：要解决的问题：提供具有小电路规模和低功耗的接收信号处理装置。解决方案：接收信号处理装置包括：混合器部分，用于将本地振荡信号与高频接收信号组合以实现频率转换; 放大部分，包括多级配置的多个可变增益放大器; 转换部分，用于将由放大部分放大的模拟信号转换为数字信号; 设置在每个可变增益放大器背面的开关; 旁路开关部分，用于设置开路/闭合一个可变增益放大器的输出沿着该路径绕过稍后的可变增益放大器以进入转换部分的路径; 用于控制开关和旁路开关部分的开关控制部分，使得每个可变增益放大器的输出绕过稍后的可变增益放大器进入转换部分; 以及DC偏移控制部分，用于根据在可变增益放大器中设置的增益设置DC偏移补偿值，以在接收到的信号绕过要校正的可变增益放大器时被校正，并且可变增益放大器的输出被校正绕过后面的可变增益放大器进入转换部分。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2010263537A Mobile communication terminal equipment, communication limiting program, program storage device, communication limiting method, and telephone directory updating method 审中-公开
标题翻译：移动通信终端设备，通信限制程序，程序存储设备，通信限制方法和电话目录更新方法
公开(公告)号：JP2010263537A
公开(公告)日：2010-11-18
申请号：JP2009114305
申请日：2009-05-11
申请人： Panasonic Corp , パナソニック株式会社
发明人： YOSHIDA KOTARO , ITO FUMIO , AKIZUKI TAIJI , SATO YUJI , SASAKI DAIZO , TAKAHASHI KENJI
IPC分类号： H04M1/00 , H04M1/2745 , H04W48/02
CPC分类号： Y02D70/00
摘要： PROBLEM TO BE SOLVED: To provide mobile communication terminal equipment for reducing power consumption and extending a stand-by time, and for preventing important communication related with a schedule from being missed.
SOLUTION: The program storage device is provided with: a communication means for performing communication such as voice call; a detection means for detecting remaining battery capacity; a scheduler for enabling a user to register a schedule; a telephone directory for registering priority information showing the priority order to each recipient; a priority information updating means for updating the priority information based on the schedule of the user registered in the scheduler and the current time; and a communication limiting means for limiting communication for each recipient based on the priority information and the remaining battery capacity. When the remaining battery capacity is small, communication with the recipient irrelevant to the schedule is suppressed.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供用于降低功耗和延长待机时间的移动通信终端设备，并且用于防止与时间表相关的重要通信被错过。解决方案：程序存储装置设置有：用于执行诸如语音呼叫的通信的通信装置; 用于检测剩余电池容量的检测装置; 用于使得用户能够注册日程表的调度器; 用于向每个接收者注册显示优先权顺序的优先信息的电话簿; 优先级信息更新装置，用于根据登记在调度器中的用户的时间表和当前时间来更新优先级信息; 以及通信限制装置，用于基于优先级信息和剩余电池容量来限制每个接收者的通信。当剩余电池容量小时，与该时间表无关的与收件人的通信被抑制。版权所有（C）2011，JPO＆INPIT

4. 发明专利

JP2009296523A Clock signal generation apparatus 审中-公开
标题翻译：时钟信号发生装置
公开(公告)号：JP2009296523A
公开(公告)日：2009-12-17
申请号：JP2008150592
申请日：2008-06-09
申请人： Panasonic Corp , パナソニック株式会社
发明人： KOSAKA MASAHIKO , ADACHI HISASHI , AKIZUKI TAIJI
IPC分类号： H03K5/151 , H03K3/02
CPC分类号： H03H11/265 , H03K5/1515 , H03K2005/00026 , H03K2005/00097
摘要： PROBLEM TO BE SOLVED: To provide a highly reliable clock signal generation apparatus capable of surely generating a biphase clock signal which absorbs temperature characteristics, power supply voltage characteristics and individual variation and has an optimal non-overlap time.
SOLUTION: The clock signal generation apparatus includes: a variable retarder for varying a delay time of a biphase clock signal to be used in a load circuit that uses a non-overlap clock signal; a non-overlap detector which detects a non-overlap time of an H-level interval in the biphase clock signal and outputs a detecting signal corresponding to the non-overlap time; and a control signal-generating section which generates a control signal for controlling the variable retarder on the basis of the detecting signal from the non-overlap detector.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种高度可靠的时钟信号发生装置，其能够可靠地生成吸收温度特性，电源电压特性和个体变化的双相时钟信号，并且具有最佳的非重叠时间。解决方案：时钟信号发生装置包括：可变延迟器，用于改变要在使用非重叠时钟信号的负载电路中使用的双相时钟信号的延迟时间; 检测双相时钟信号中的H电平间隔的非重叠时间的非重叠检测器，并输出与非重叠时间对应的检测信号; 以及控制信号生成部，其基于来自所述非重叠检测器的检测信号生成用于控制所述可变延迟器的控制信号。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2013247469A Amplifier circuit 审中-公开
标题翻译：放大器电路
公开(公告)号：JP2013247469A
公开(公告)日：2013-12-09
申请号：JP2012118920
申请日：2012-05-24
申请人： Panasonic Corp , パナソニック株式会社
发明人： AKIZUKI TAIJI , MATSUO MICHIAKI
IPC分类号： H03F3/193 , H03F1/22
摘要： PROBLEM TO BE SOLVED: To provide an amplifier circuit providing an improved gain.SOLUTION: The amplifier circuit having plural amplifier elements which are cascade-connected to each other includes: a distribution control section that distributes an input signal, outputs a first distribution signal from a first output terminal, and outputs a second distribution signal of an amplitude different from the amplitude of the first distribution signal from a second output terminal; a first amplifier element with a second terminal grounded, which inputs the first distribution signal to a first terminal, and outputs a first amplified signal which is the amplified first distribution signal from a third terminal; and a second amplifier element that inputs the second distribution signal to a first terminal as a bias input, inputs the first amplified signal to a second terminal, and outputs a second amplified signal of the amplified first amplified signal from a third terminal. The phase of the first distribution signal has the same phase as the phase of the second distribution signal.
摘要翻译：要解决的问题：提供一种提供改善的增益的放大器电路。解决方案：具有彼此串联连接的多个放大器元件的放大器电路包括：分配控制部分，其分配输入信号，输出来自第一输出端子，并输出与第一分配信号的振幅不同的幅度的第二分配信号来自第二输出端子; 第一放大器元件，其具有第二端子接地，其将第一分配信号输入到第一端子，并且从第三端子输出作为放大的第一分配信号的第一放大信号; 以及将第二分配信号输入到作为偏置输入的第一端子的第二放大器元件，将第一放大信号输入到第二端子，并从第三端子输出放大的第一放大信号的第二放大信号。第一分配信号的相位与第二分配信号的相位具有相同的相位。

6. 发明专利

JP2011229073A Gain variation compensator 审中-公开
标题翻译：增益补偿器
公开(公告)号：JP2011229073A
公开(公告)日：2011-11-10
申请号：JP2010098929
申请日：2010-04-22
申请人： Panasonic Corp , パナソニック株式会社
发明人： KOBAYASHI MASASHI , AKIZUKI TAIJI , SHIMA TAKAHIRO
IPC分类号： H03F1/30
摘要： PROBLEM TO BE SOLVED: To provide a gain variation compensator which compensates for variation in gain by controlling an amount of current flowing to an amplifier circuit even if a voltage provided by a voltage source varies.SOLUTION: A gain variation compensator 100 includes: an amplifier circuit 110 which amplifies an input signal using a voltage provided by a voltage source 111 and a constant current source; a source voltage variation detection unit 120 which detects variation in voltage provided by the voltage source 111; and a current variable circuit 130 which controls the amount of current flowing to the amplifier circuit 110 in accordance with an amount of the variation in voltage detected by the source voltage variation detection unit 120. The gain variation compensator 100 has the current variable circuit 130 connected in parallel with a constant current source transistor of the amplifier circuit 110 or a differential circuit thereof, and supplies the current to the current variable circuit 130 in advance to detect the variation in source voltage by the source voltage variation detection unit 120. The current variable circuit 130 controls the amount of current flowing to the amplifier 110 by adjusting the amount of current in accordance with the amount of voltage variation.
摘要翻译：要解决的问题：提供一种增益变化补偿器，其通过控制流向放大器电路的电流量来补偿增益的变化，即使电压源提供的电压变化。增益变化补偿器100包括：放大器电路110，其使用由电压源111和恒定电流源提供的电压来放大输入信号; 源电压变化检测单元120，其检测由电压源111提供的电压的变化; 以及电流可变电路130，其根据源电压变化检测单元120检测到的电压变化量来控制流向放大器电路110的电流量。增益变化补偿器100具有连接的电流可变电路130 与放大器电路110的恒流源晶体管或其差分电路并联，并且预先将电流提供给电流可变电路130，以检测源极电压变化检测单元120的源极电压的变化。当前变量电路130通过根据电压变化量调节电流量来控制流向放大器110的电流量。版权所有（C）2012，JPO＆INPIT

7. 发明专利

JP2011009968A Mobile terminal device and charging control method 审中-公开
标题翻译：移动终端设备和充电控制方法
公开(公告)号：JP2011009968A
公开(公告)日：2011-01-13
申请号：JP2009150295
申请日：2009-06-24
申请人： Panasonic Corp , パナソニック株式会社
发明人： AKIZUKI TAIJI , YOSHIDA KOTARO , ITO FUMIO , SATO YUJI , TAKAHASHI KENJI , SASAKI DAIZO
IPC分类号： H04M1/00 , H04M1/247
摘要： PROBLEM TO BE SOLVED: To provide a mobile terminal device and a charging control method, capable of preserving more incoming call logs, preventing a delay of notification to a party associated with an incoming call log, and preventing current consumption by a plurality of times of needless call requests from the same incoming call party.SOLUTION: A mobile phone 100 includes a radio unit 110, a control unit 120, a memory 130, a power supply 140, and a notification unit 150. When a remaining capacity of a battery detected by a battery power detection circuit 142 of the power supply 140 comes to a predetermined value or less, the control unit 120 leaves the incoming call log as it is, and sets the OFF mode for non-communication and then transmits a call termination character indicating that no call is available because of battery shutoff to an incoming call party.
摘要翻译：要解决的问题：为了提供能够保留更多来电日志的移动终端设备和计费控制方法，防止对与呼入日志相关联的一方的通知的延迟，并且防止电流消耗多次移动电话100包括无线电单元110，控制单元120，存储器130，电源140和通知单元150.当检测到电池的剩余容量时通过电源140的电池电力检测电路142达到规定值以下，控制部120按原样离开来电记录，并且设定非通信的OFF模式，然后发送指示由于电池关闭到来电方，因此无可用电话。

8. 发明专利

JP2010004425A Clock signal generating device and discrete-time type circuit 审中-公开
标题翻译：时钟信号发生器和分离型电路
公开(公告)号：JP2010004425A
公开(公告)日：2010-01-07
申请号：JP2008162870
申请日：2008-06-23
申请人： Panasonic Corp , パナソニック株式会社
发明人： AKIZUKI TAIJI , KOSAKA MASAHIKO , ADACHI HISASHI
IPC分类号： H03K5/15 , H03K5/135
CPC分类号： H03K5/135 , H03K5/133 , H03K5/1515 , H03K2005/00234
摘要： PROBLEM TO BE SOLVED: To provide a clock signal generating device capable of setting optimally a non-overlap time, that a discrete-time type circuit requires, and a duty ratio of a clock signal in the case that the clock signal required in the discrete-time type circuit is varied by an external variation factor such as power supply voltage or environmental temperature. SOLUTION: In the clock signal generating device, a clock signal delay calculation section calculates a delay amount of an N-phase clock signal by including a delay detection circuit for monitoring delay characteristics caused by an external variation factor in a variable delay circuit of a clock signal generation circuit, and a clock signal delay control section is configured to vary the delay amount in the variable delay circuit on the basis of delay variation data, stored in a delay variation data section, with the external variation factor as a parameter and the calculated delay amount of the N-phase clock signal. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种时钟信号发生装置，其能够最佳地设定离散时间型电路所需的非重叠时间，并且在需要时钟信号的情况下能够设置时钟信号的占空比离散时间型电路由外部变化因素（如电源电压或环境温度）而变化。解决方案：在时钟信号发生装置中，时钟信号延迟计算部分通过包括用于监视由可变延迟电路中的外部变化因子引起的延迟特性的延迟检测电路来计算N相时钟信号的延迟量并且时钟信号延迟控制部分被配置为基于存储在延迟变化数据部分中的延迟变化数据，以外部变化因子作为参数来改变可变延迟电路中的延迟量和计算出的N相时钟信号的延迟量。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2013030934A Power division circuit 有权
标题翻译：电源部门电路
公开(公告)号：JP2013030934A
公开(公告)日：2013-02-07
申请号：JP2011164742
申请日：2011-07-27
申请人： Panasonic Corp , パナソニック株式会社
发明人： AKIZUKI TAIJI , SATO JUNJI
IPC分类号： H03H7/48 , H01P5/10 , H03F3/189 , H03F3/45 , H04B1/18
CPC分类号： H02J3/00 , H01P5/12 , H03F3/211 , H03F3/45085 , H03F3/45183 , H03F2200/06 , H03F2200/192 , H03F2200/204 , H03F2200/411 , H03F2200/534 , H03F2200/537 , H03F2200/541 , H03F2203/45644 , H03F2203/45702 , H03F2203/45731 , H03H7/09 , H03H7/42 , Y10T307/305
摘要： PROBLEM TO BE SOLVED: To reduce a circuit error between differential output signals when inputting a differential input signal and outputting a pair of differential output signals.SOLUTION: A power division circuit 10 includes transformers 2A, 2B and an addition circuit 3. Output signals of the transformer 2A are output as differential signals comprising a normal phase signal (Vout2Ap) with a phase of θ1+90° and a reverse phase signal (Vout2An) with a phase of θ1-90°. Output signals of the transformer 2B are output as differential signals comprising a normal phase signal (Vout2Bp) with a phase of θ2+90° and a reverse phase signal (Vout2Bn) with a phase of θ2-90°. The addition circuit 3 performs vector additions of the normal phase signals and of the reverse phase signals to combine the two pairs of differential signals from the transformers 2A, 2B into one pair of differential output signals. The differential output signals are signals compensated for a phase error (θ1-θ2) caused in the transformers 2A, 2B.
摘要翻译：要解决的问题：当输入差分输入信号并输出一对差分输出信号时，减小差分输出信号之间的电路误差。功率分配电路10包括变压器2A，2B和加法电路3.变压器2A的输出信号作为差分信号输出，该差分信号包括相位为θ1+ 90°的正相信号（Vout2Ap）和反相信号（Vout2An），相位为θ1-90°。输出变压器2B的输出信号作为包含相位为θ2+ 90°的正相信号（Vout2Bp）和相位为θ2-90°的反相信号（Vout2Bn）的差分信号。加法电路3执行正常相位信号和反相信号的向量相加，以将来自变压器2A，2B的两对差分信号组合成一对差分输出信号。差分输出信号被补偿在变压器2A，2B中引起的相位误差（θ1-θ2）。版权所有（C）2013，JPO＆INPIT

10. 发明专利

JP2012205250A Ad conversion device 有权
标题翻译： AD转换器件
公开(公告)号：JP2012205250A
公开(公告)日：2012-10-22
申请号：JP2011070508
申请日：2011-03-28
申请人： Panasonic Corp , パナソニック株式会社
发明人： AKIZUKI TAIJI , FUJITA TAKU
IPC分类号： H03M1/20 , H03M1/12
CPC分类号： H03M1/20 , H03M1/201
摘要： PROBLEM TO BE SOLVED: To provide an AD conversion device that implements improved resolution of digital output without changing the operating frequency and bit number of an AD conversion section without increasing circuit scale and current consumption.SOLUTION: The AD conversion device includes: a control clock generation section for generating a control clock having a period that is an integral multiple of the period of a reference clock; a shift voltage generation section for generating a different shift voltage in each period of the reference clock such that the period of the control clock is one cycle; an offsetting section for offsetting an analog signal by the shift voltage; the AD conversion section for AD-converting the offset analog signal in each period of the reference clock; and an averaging section for averaging an output of the A/D conversion section in each period of the control clock. The shift voltage is based on a reference shift value, so that the sum of a minimum resolution value of output of the averaging section and an offset value of the shift voltage in the period of the reference clock is a minimum resolution value of the AD conversion section, and is different in each period of the reference clock.
摘要翻译：要解决的问题：提供一种在不改变AD转换部分的工作频率和位数而不增加电路规模和电流消耗的情况下实现数字输出的改进的分辨率的AD转换装置。解决方案：AD转换装置包括：控制时钟产生部分，用于产生具有作为参考时钟的周期的整数倍的周期的控制时钟; 移位电压产生部分，用于在参考时钟的每个周期中产生不同的移位电压，使得控制时钟的周期为一个周期; 用于通过移位电压抵消模拟信号的偏移部分; AD转换部分，用于在参考时钟的每个周期中对偏移模拟信号进行AD转换; 以及平均部分，用于在控制时钟的每个周期中平均A / D转换部分的输出。移位电压基于参考移位值，使得平均化部分的输出的最小分辨率值与基准时钟周期内的移位电压的偏移值的和是AD转换的最小分辨率值部分，并且在参考时钟的每个周期中是不同的。版权所有（C）2013，JPO＆INPIT

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