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1. 发明专利

JP2007272127A Semiconductor integrated circuit device, shift register circuit, and driving circuit for display device 有权
标题翻译：半导体集成电路装置，移位寄存器电路和显示装置的驱动电路
公开(公告)号：JP2007272127A
公开(公告)日：2007-10-18
申请号：JP2006100646
申请日：2006-03-31
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： UEDA TOSHIAKI
IPC分类号： G09G3/36 , G02F1/133 , G09G3/20 , G11C19/28
CPC分类号： G09G3/3688 , G09G3/3648 , G09G2330/06 , G11C19/00 , G11C19/28
摘要： PROBLEM TO BE SOLVED: To lighten the load on a signal wiring in a chip without using a complicated control circuit. SOLUTION: Shift registers 110 and data registers 120 are divided into two blocks on a front-stage side and a rear-stage side, and paths of clock lines CL to the shift registers 110 and data lines DL to the data registers 120 are branched into two paths from the centers of the two blocks to the front-stage side and rear-stage side to be separated through gate circuits 170a and 170b, and 180a and 180b. Then the respective gate circuits are inhibited from outputting with inversion signals /SP3 to /SP5 of shift pulses SP2 to SP4 and shift pulses SP3 to SP5. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：在不使用复杂的控制电路的情况下减轻芯片中的信号布线的负载。解决方案：移位寄存器110和数据寄存器120在前级侧和后级侧被分成两个块，并且时钟线CL到移位寄存器110和数据线DL到数据寄存器120的路径被分支成从两个块的中心到前级侧和后侧的两条路径，以通过门电路170a和170b以及180a和180b分离。然后，禁止各个门电路输出与移位脉冲SP2至SP4和移位脉冲SP3至SP5的反相信号/ SP3至/ SP5。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2005316209A Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路设备
公开(公告)号：JP2005316209A
公开(公告)日：2005-11-10
申请号：JP2004134940
申请日：2004-04-30
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： UEDA TOSHIAKI
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36 , H03K19/00 , H03K19/0175
CPC分类号： G09G3/2096 , G09G3/3688 , G09G2310/027 , G09G2330/06
摘要： PROBLEM TO BE SOLVED: To return a receiver for data at a high speed without variation in a bias potential to a receiver for a clock signal when returning the receiver for data to a stationary operational state from a halt state.
SOLUTION: In a receiver 20 constituting a semiconductor integrated circuit, a bias circuit 25 has a 1st bias potential output Vb1 to the 1st receiver 21 for the clock signal and a 2nd bias potential output Vb2 to each 2nd receiver 22 for display data, and the output Vb1 is derived via 1st bias wiring 26 and the output Vb2 is derived via 2nd bias wiring 27, and each switch 24 is connected across the 2nd bias wiring 27 and each 2nd receiver 22. The output Vb1 is at a stationary bias potential, and the output Vb2 is at a high bias potential for a predetermined period from ON-control by the switch 24, and is made to the stationary bias potential after the predetermined period.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：当将数据的接收机从停止状态返回到静止操作状态时，为了将时钟信号的接收器的偏置电位的偏置电位没有变化地返回到数据的接收器。解决方案：在构成半导体集成电路的接收器20中，偏置电路25具有用于时钟信号的第一接收器21的第一偏置电位输出Vb1和用于显示数据的每个第二接收器22的第二偏置电位输出Vb2 ，并且经由第一偏置布线26导出输出Vb1，并且经由第二偏置布线27导出输出Vb2，并且每个开关24跨越第二偏置布线27和每个第二接收器22连接。输出Vb1处于静态偏置电位，并且输出Vb2在由开关24的接通控制的预定时间段内处于高偏置电位，并且在预定时段之后变为固定偏置电位。版权所有（C）2006，JPO＆NCIPI

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