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1. 发明专利

JPH04243146A FAILURE-ANALYZING METHOD OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04243146A
公开(公告)日：1992-08-31
申请号：JP414691
申请日：1991-01-18
申请人： NEC CORP
发明人： MURASE MASAMICHI
IPC分类号： G01R31/00 , H01L21/66
摘要： PURPOSE:To make a failure analysis possible without changing element characteristic by providing an opening between the layers of upper layer conductor wiring and multilayer conductor wiring and by connecting a wiring by means of tungsten film with a lower layer wiring and extending and drawing out the tungsten wiring to the outside of the upper layer wiring. CONSTITUTION:The two-layer wiring of aluminum 3 and gold 5 is formed by the use of a silicon nitride film 4 as a layer film. A hole is made in the gold wiring 5 and the silicon nitride film 4 is provided with an opening 6 by the use of a focused ion beam(FIB) apparatus. A tungsten wiring is formed in the opening 6 so as to be connected with the aluminum wiring 3. The separated parts of the gold wiring 5 are connected onto the gold wiring 5 on both sides of the opening 6 by the use of a gold ribbon 8 in the manner of avoiding the opening 6. The electron beam of a tester is applied onto the tungsten wiring. Thus, a failure analysis is made possible without changing element characteristics and without being affected by a local electric field effect through an upper layer winding.

2. 发明专利

JPH04162546A ANALYZING METHOD FOR FAULT OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04162546A
公开(公告)日：1992-06-08
申请号：JP28879490
申请日：1990-10-25
申请人： NEC CORP
发明人： MURASE MASAMICHI
IPC分类号： G01R31/00 , G01R31/302 , H01L21/66
摘要： PURPOSE:To analyze a fault without changing element characteristics by a method wherein an upper-layer conductor wiring in a superposing section with a lower-layer conductor wiring is removed, an inter-layer insulating film in the upper-layer conductor wiring is removed, a hole is bored so that one part of the lower-layer conductor wiring is exposed, and the partially cut upper-layer conductor wiring is re-connected while avoiding the hole. CONSTITUTION:When a lower-layer conductor wiring 3 at a position, where the lower- layer conductor wiring 3 and an upper-layer conductor wiring 3 are superposed, in multilayer conductor wirings on a semiconductor integrated circuit is analyzed, the upper-layer conductor wiring 3 in the superposing section of said lower-layer conductor wiring 3 and the upper-layer conductor wiring 3 is removed, an inter-layer insulating film 4 in said superposing section exposed through the removing process is taken off, and a hole 5 is bored partially to the inter-layer insulating film 4 so that one part of the lower-layer conductor wiring 3 is exposed to a surface. The partially cut upper-layer conductor wiring 3 through said boring process is re-connected 7 so as to avoid said hole 5, and electron beams 8 are applied to the surface section of the lower-layer conductor wiring 3 exposed to a surface through said boring process and the potential is measured by an electron beam tester using a stroboscopic scanning type electron microscope and a fault is analyzed.

3. 发明专利

JPH02100336A TROUBLE-SHOOTING OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02100336A
公开(公告)日：1990-04-12
申请号：JP25417288
申请日：1988-10-07
申请人： NEC CORP
发明人： MURASE MASAMICHI
IPC分类号： G01R31/26 , G01R31/302 , H01L21/66
摘要： PURPOSE:To assure observation of a waveform on a wiring in interest without being affected by an adjacent signal wiring exhibiting a large potential difference with respect to the wiring in interest by forming a partial opening through an insulating film by the use of an FIB device, forming a conductor pad of the FIB device, and forming a partial insulating film around the conductor pad using the FIB device. CONSTITUTION:An insulating film 4 for passivation on a wiring to be trouble- shot and an interlayer insulating film of a multilayered conductor wiring are removed by FIB(focused ion beam) etching to form an opening section 5. After exposing part of the wiring 3, a tungsten film 6 is formed in the opening section 5 and around the same by FIB, and an insulating film is formed in the vicinity of a tungsten pad on other wirings, excepting the portion to be trouble-shot, adjacent to the tungsten film 6. Hereby, only a potential waveform on the tungsten pad led out from the wiring to be trouble-shot can be observed for trouble-shooting through an electron beam tester without being affected by potential changes on surrounding wirings.

4. 发明专利

JPS63229735A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63229735A
公开(公告)日：1988-09-26
申请号：JP6465487
申请日：1987-03-18
申请人： NEC CORP
发明人： MURASE MASAMICHI
IPC分类号： H01L29/43 , H01L21/28 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L23/52 , H01L27/04
摘要： PURPOSE:To reduce a resistor forming process, to easily form polysilicon resistors and to make it possible to easily form various polysilicon resistors, each having different sheet resistance in the same layer, by providing the polysilicon resistors in contacts of a semiconductor integrated circuit or in interlayer through-holes of a multilayer interconnection. CONSTITUTION:First wiring layers 5, each consisting of a two-layer structure of an Al layer 3 and a tungsten silicide layer 4, are formed on an Si oxide film 2 on an n-type Si substrate 1, a plasma nitride film 6 is formed thereon and through holes 7 are formed in the film 6. Among them are some through holes 7 packed with Al 3 or tungsten 4 and p-type polysilicon 8 is packed in the residual through holes 7 to form polysilicon resistors. Thereby, a resistor forming process is reduced and the polysilicon resistors can be easily obtained.

5. 发明专利

JPS5941851A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS5941851A
公开(公告)日：1984-03-08
申请号：JP15205282
申请日：1982-09-01
申请人： Nec Corp
发明人： MURASE MASAMICHI
IPC分类号： H01L21/822 , H01L21/265 , H01L21/316 , H01L21/331 , H01L21/76 , H01L21/762 , H01L27/04 , H01L29/73
CPC分类号： H01L21/76221
摘要： PURPOSE:To obtain a compact device with high density, by the method including a process which removes an oxide film, a process which makes an insulating film thin, a process which forms a region including high concentration impurities, and a process which forms an element. CONSTITUTION:On a P type silicon substrate 301, a silicon oxide film 304 (LPCVD) and a silicon nitride film 305 are formed. Thereafter, a silicon oxide film 306 and a plasma CVD (PCVD) silicon nitride film 307 are formed. Then the thick silicon nitride film is removed. Thereafter, only the thick PCVD silicon nitride film 307 on the region 308, which reduces the potential of the P type silicon substrate 301 to the lowest potential, is selectively removed. Energy and the dose amount of ion implantation are selected. and P type impurity ions are implanted. Then, with the thick PCVD silicon nitride film 307 and the thin LPCVD silicon nitride film 305 as a mask, a thick silicon oxide film 311 is formed. Thereafter, on a P type epitaxial silicon layer 302 in an element forming region, a collector compensating region 313, a base region 314, an emitter region 315, an interlayer insulating film 316, and an aluminum wiring 317 are formed.
摘要翻译：目的：为了获得高密度的紧密装置，通过包括除去氧化膜的方法，使绝缘膜变薄的方法，形成包含高浓度杂质的区域的方法和形成元素的方法。构成：在P型硅衬底301上形成氧化硅膜304（LPCVD）和氮化硅膜305。此后，形成氧化硅膜306和等离子体CVD（PCVD）氮化硅膜307。然后去除厚的氮化硅膜。此后，仅选择性地去除将P型硅衬底301的电位降至最低电位的区域308上的厚PCVD氮化硅膜307。选择能量和离子注入的剂量。并注入P型杂质离子。然后，利用厚的PCVD氮化硅膜307和薄的LPCVD氮化硅膜305作为掩模，形成厚的氧化硅膜311。此后，在元件形成区域中的P型外延硅层302上形成集电极补偿区域313，基极区域314，发射极区域315，层间绝缘膜316和铝布线317。

6. 发明专利

JPS5723224A Manufacture of semiconductor integrated circuit 失效
标题翻译：半导体集成电路的制造
公开(公告)号：JPS5723224A
公开(公告)日：1982-02-06
申请号：JP9857380
申请日：1980-07-18
申请人： Nec Corp
发明人： MURASE MASAMICHI
IPC分类号： H01L21/3205 , H01L21/28 , H01L21/283
CPC分类号： H01L21/283
摘要： PURPOSE:To prevent disconnection when a wiring layer of metal thin film for a semiconductor integrated circuit is to be formed by a method wherein the metal thin film is formed preliminary only inside of an opening for terminal to reduce difference of the step part. CONSTITUTION:A resist mask 67 is applied to an SiO2 layer 63 on an si substrate 61 and the opening is formed, and the metal thin films 65, 68 are adhered on the whole surface. The opening 74 is buried with the metal thin film 75 by the lift off technique. The metal thin film is laminated thereon, and selective etching is performed to form the wiring layer 87. Accordingly because the opening for terminal is buried with the metal layer and step part is reduced, disconnection of wiring is reduced, and the device having high reliability can be obtained.
摘要翻译：目的：为了防止在半导体集成电路用金属薄膜的布线层通过以下方法形成金属薄膜时，断开连接，其中金属薄膜仅在端子的开口内形成，以减小台阶部分的差异。构成：将抗蚀剂掩模67施加到Si基板61上的SiO 2层63，并且形成开口，并且金属薄膜65,68粘附在整个表面上。通过剥离技术将开口74与金属薄膜75一起埋设。金属薄膜层叠在其上，进行选择性蚀刻以形成布线层87.因此，由于端子的开口被金属层和台阶部分埋入，因此布线的断开被降低，并且具有高可靠性的装置可以获得。

7. 发明专利

JPH0574890A FAILURE ANALYTICAL METHOD OF SEMICONDUCTOR DEVICES 失效
公开(公告)号：JPH0574890A
公开(公告)日：1993-03-26
申请号：JP23758691
申请日：1991-09-18
申请人： NEC CORP
发明人： MURASE MASAMICHI
IPC分类号： G01R31/26 , G01R31/302 , H01L21/66
摘要： PURPOSE:To analyze operational failures without changing device characteristics and undergoing local field effect induced by an upper layer wiring by allowing electron beams of an electron beam tester to apply to the top of an extension of a lower layer wiring and measuring the potential. CONSTITUTION:The electron beams of an electron beam tester which uses a stroboscope are emitted on a tungsten wiring 7 pulled out from a first layer aluminum wiring 3 in an opening section 6 so that the electron beams may strike at the top of the tungsten wiring 7 properly. This construction makes it possible to measure the potential of the first layer wiring 3 covered with a second layer wiring 5 without undergoing any local electric field effect of a second layer gold wiring 5 and hence analyze operational failures properly.

8. 发明专利

JPH02226079A METHOD FOR ANALYZING SEMICONDUCTOR DEVICE FAILURE 失效
公开(公告)号：JPH02226079A
公开(公告)日：1990-09-07
申请号：JP4716389
申请日：1989-02-27
申请人： NEC CORP
发明人： MURASE MASAMICHI
IPC分类号： G01R31/302 , H01L21/66
摘要： PURPOSE:To enable potential of lower wiring to be measured by a method wherein a hole is formed on an insulation film where lower layer conductor wiring and upper layer conductor wiring are laid while electron beam is radiated to a side of the lower layer conductor wiring partially exposed to the surface to measure the potential on this part by an electron beam tester to make analysis. CONSTITUTION:When a semiconductor integrated circuit on a substrate 1 for example formed with aluminum wiring 3 by using silicone nitride films 4 as an interlayer film and a passivation film is to be analyzed, a hole 5 is formed on the silicon nitride film 4 so that a side of the aluminum wiring 3 of a first layer to be analyzed is exposed on the surface by using a focused ion beam (FIB) apparatus. Then electron beam of an electron beam tester using a strobe apparatus is radiated to the substrate 1 from a slant direction so that the beam is incident to the hole 5 while the electron beam is applied to the side of the aluminum wiring 3 of the first layer. This allows the first layer aluminum wiring 3 covered with the second layer aluminum wiring 3 to be measured by potential.

9. 发明专利

JPH01218047A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01218047A
公开(公告)日：1989-08-31
申请号：JP4502088
申请日：1988-02-26
申请人： NEC CORP
发明人： MURASE MASAMICHI
IPC分类号： H01L21/316 , G01R31/28 , G01R31/302 , H01L21/31 , H01L21/318 , H01L21/66
摘要： PURPOSE:To easily detect the value of a potential in a multilayer interconnection structure by a method wherein a part directly on a conductor wiring part is formed by an insulating film which is partially different from another film and the thickness between the different insulating film and the conductor wiring part in its layer is made equal to the thickness of the insulating film directly on the conductor wiring part in an uppermost layer. CONSTITUTION:A silicon oxide film 2 is formed on a silicon substrate 1; a first aluminum wiring part 3 is formed on it. A silicon oxide film 6 is formed partially only on the wiring part 3 instead of a silicon nitride film 4. The thickness of the nitride film 4 between the oxide film 6 and the wiring part 3 is made equal to the thickness of the nitride film 4 on a second aluminum wiring part 5. When an electron beam tester is used, only the oxide film 6 on the wiring part 3 is etched and removed; the thickness of the nitride film 4 on the wiring part 3 is made equal to that on the wiring part 5; potentials are compared under an identical condition. By this setup, the value of the potentials in a multilayer interconnection structure can be detected easily.

10. 发明专利

JPH01119037A TROUBLESHOOTING OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01119037A
公开(公告)日：1989-05-11
申请号：JP27638887
申请日：1987-10-30
申请人： NEC CORP
发明人： MURASE MASAMICHI
IPC分类号： H01L21/66 , G01R31/26 , G01R31/302
摘要： PURPOSE:To easily troubleshoot potential differences in the order of micron using an electron beam tester by removing passivation and interlayer insulating films by means of a reactive ion etching(RIE), and removing the remaining insulating films by means of a focused ion beam(FIB) etching. CONSTITUTION:When troubleshooting a semiconductor integrated circuit in which silicon nitride films 4 are used as interlayer and passivation films for double layer wiring in aluminum, the silicon nitride films 4 are anisotropically etched by RIE, and the silicon nitride films 4 remaining on the aluminum wiring 3 of both first and second layers are removed by FIB etching. Then a troubleshooting is performed by an electron beam tester.

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