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1. 发明专利

JPS56116339A AUTOMATIC EQUALIZER 失效
公开(公告)号：JPS56116339A
公开(公告)日：1981-09-12
申请号：JP2002780
申请日：1980-02-19
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE
发明人： YAMAGUCHI MASARU , KOYAMA TOORU , AKASHI FUMIO , WAKAHARA TOSHIHIKO
IPC分类号： H04B3/06 , H03H11/04 , H04L25/03
摘要： PURPOSE:To reduce the interference between codes, by controlling the gain of the emphasis circuit with the output of the 2nd peak detection circuit, in the automatic equalizer compensating the base band transmission loss. CONSTITUTION:If any interference between codes is taken place at the output of a variable gain circuit 2 controlling the flat gain, when the output level of peak voltage detection circuits 71-7N is greater than the reference voltage Vref, the output of control circuits 8a-8N is smaller, resulting in that the gain of emphasis circuits 91-9N is increased. Conversely, if smaller than the reference voltage Vref, the gain of emphasis circuits 91-9N is increased. Thus, the output of the emphasis circuit 9N removes the interference between codes.

2. 发明专利

JPS56109012A AUTOMATIC GAIN CONTROL CIRCUIT 失效
公开(公告)号：JPS56109012A
公开(公告)日：1981-08-29
申请号：JP1122180
申请日：1980-02-01
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE
发明人： KOYAMA TOORU , YAMAGUCHI MASARU , AKASHI FUMIO , WAKAHARA TOSHIHIKO
IPC分类号： H03G3/30 , H03G3/20
摘要： PURPOSE:To decrease the return time at steady-state, by limiting the amplitude from the limiter when an input signal is rapidly increased from the limiter and a surge is input to the input. CONSTITUTION:The input signal from the line (a) is amplified by the gain determined with the level of the line (d) with a variable gain control amplifier 1 and becomes the output signal of (b). When the output signal level of (b) is increased than the level of the line (c), a current flows to a resistor 2 and a diode 3, a capacitor 4 is charged with the time constant determined with the resistor 2, and the level of the line (c) is increased, the output (d) of an amplifier 7 is increased and the gain of the amplifier 1 is decreased. In this case, a limiter 8 is provided which makes limit with a slightly higher level than the reference voltage, allowing the limiter 8 to limit the amplitude, if the input signal is rapidly increased and a surge is input to the input. Thus, the capacitor 4 is charged to a slightly higher value than the reference voltage, allowing to reduce the time returned at the steady-state.

3. 发明专利

JPS5717252A LINE TERMINATOR 失效
公开(公告)号：JPS5717252A
公开(公告)日：1982-01-28
申请号：JP9164880
申请日：1980-07-07
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO
发明人： SHIMADA MASAHARU , YAMAGUCHI MASARU
IPC分类号： H04M11/06 , H04L5/22 , H04L5/24 , H04L29/02 , H04M11/00
摘要： PURPOSE:To reduce the cost, by using an interface circuit which can respectively correspond to telephone sets, facsimile terminals, and data terminals and making digital base band transmission. CONSTITUTION:When the output of comparison circuits 5212, 5213, 5214, 5215 is zero, the output of read-only memories 5220, 5221, 5222, 5223 is zero. D1 is outputted from multi-input selectors 5225, 5226 when S1 is at 1 and DN is outputted when SN is at 1. When S1-SN or SN+1 are at 0, the output is zero. Thus, multi- plex frame can be constituted by taking the logical sum of the outputs of the multi- input selectors 5225, 5226 and read-only memories 5220, 5221, 5222, 5223, 5224 at a logical sum circuit 5227.

4. 发明专利

JPS5717250A LINE TERMINATOR 失效
公开(公告)号：JPS5717250A
公开(公告)日：1982-01-28
申请号：JP9164680
申请日：1980-07-07
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO
发明人： SHIMADA MASAHARU , YAMAGUCHI MASARU
IPC分类号： H04M11/06 , G11B21/04 , H04L5/22 , H04L5/24 , H04L29/02 , H04M11/00
摘要： PURPOSE:To make time division and multiplex of information from each terminal and to achieve the effective use of subscriber lines, by using interface circuits which can respectively correspond to telephone sets, facsimile terminals and data terminals. CONSTITUTION:The information transmitted from data terminals, facsimile terminals and telephone sets is inputted to an interface circuit 40 via terminals 1, 2, 3. Input and output terminals with the N-th terminal are denated by 3. The interface circuit 40 makes logical and electric level conversion to the information from each terminal. The output of the interface circuit 40 is inputted to a buffer memory circuit 50 in a code converter section 5. The buffer memory circuit 50 temporarily stores the control information. A multiplex circuit 52 is a circuit converting the service information, control information, frame code into a corresponding frame construction, and a transmission timing generating circuit 51 is a circuit supplying required clock to each part.

5. 发明专利

JPS5461408A BAND COMPRESSION CIRCUIT FOR FACSIMILE SIGNAL 失效
公开(公告)号：JPS5461408A
公开(公告)日：1979-05-17
申请号：JP12847377
申请日：1977-10-25
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE
发明人： YAMAGUCHI MASARU , JINBOU YOSHIHIRO , SUZUKI YUTAKA
IPC分类号： H04B1/66 , H04N1/00 , H04N1/409
摘要： PURPOSE:To perform band compression so that no discontinuity is caused for signal, by detecting the minimum point of the facsimile signal and by inverting only the polarity of signal for the polarity before the minimum point when the signal is smaller than the reference value. CONSTITUTION:The facsimile signal A is inputted to the input terminal 1. The emphasis circuit 2 judges the signal A for the threshold value from the reference value, performing weighting. The wave processing circuit 3 detects the minimum point of the signal B, and if it is smaller than the reference value, the polarity conversion signal C inverting the polarity is formed, and the circuit 3 delivers the facsimile signal D in which it is in agreement with the signal B for the level other than at the time near the signal inversion and no discontinuity if caused for the level near the time of inversion. Since the level is not discontinuous even with the inversion of facsimile signal level every minimum point, no spread for the occupying band is caused.

6. 发明专利

JPS5711543A AUTOMATIC EQUALIZER 失效
公开(公告)号：JPS5711543A
公开(公告)日：1982-01-21
申请号：JP8538080
申请日：1980-06-24
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE
发明人： YAMAGUCHI MASARU , KOYAMA TOORU , AKASHI FUMIO , WAKAHARA TOSHIHIKO , SHIMADA MASAHARU
IPC分类号： H03H21/00 , H04B3/06 , H04L25/03
摘要： PURPOSE:To reduce the interference between codes, by detecting a peak voltage of a tuning circuit output and controlling the gain in the frequency at an emphasis circuit depending on the comparison between the peak voltage and the reference voltage. CONSTITUTION:If the interference between codes is produced in an output of an adder 5, deficient or excessive output level is caused for peack voltage detecting circuits 71, 72-7N. If this output level is greater than the reference voltage Vref, the output of control circuits 81, 82-8N is smaller, resulting that the gain of emphasis circuits 91, 92-9N is smaller. Inversely, if the output level of peak voltage detecting circuits 71, 72-7N smaller than the referenve voltage Vref, the output of the control circuits 81, 82-8N is greater, resulting that the gain of emphasis circuits 91, 92-9N is greater. Thus, with the control like this, thein terference between codes can be rejected with the output of the emphasis circuit 9N.

7. 发明专利

JPS56120232A AUTOMATIC EQUALIZER 失效
公开(公告)号：JPS56120232A
公开(公告)日：1981-09-21
申请号：JP2477480
申请日：1980-02-28
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE
发明人： YAMAGUCHI MASARU , KOYAMA TOORU , AKASHI FUMIO , WAKAHARA TOSHIHIKO , SHIMADA MASAHARU
IPC分类号： H03H21/00 , H04B3/06 , H04L25/03
摘要： PURPOSE:To increase the performance of an automatic equalizer, by inputting an input signal to a plurality of tuning circuits and controlling the gain of emphasis circuit with each peak voltage output of each tuning circuit. CONSTITUTION:An input signal 1 is applied to a variable gain control circuit 2 and control is made that the peak level of the output of the circuit 2 can be constant at a peak voltage detecting circuit 10. The output of the circuit 2 is applied to a plurality of tuning circuits 61-6N having different center frequency. The output of the tuning circuits 61-6N controls a plurality of emphasis circuits 91-9N having different center frequency via peak voltage detecting circuits 71-7N and control circuits 81-8N. Thus, since the tuning circuit and emphasis circuit are provided every frequency, the interference between signals is decreased and the characteristics of the equalizer can be increased.

8. 发明专利

JPS5461410A MODULATION CIRCUIT FOR FACSIMILE SIGNAL 失效
公开(公告)号：JPS5461410A
公开(公告)日：1979-05-17
申请号：JP12847277
申请日：1977-10-25
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE
发明人： YAMAGUCHI MASARU , JINBOU YOSHIHIRO , SUZUKI YUTAKA
IPC分类号： H04N1/40
摘要： PURPOSE:To prevent the discontinuity in signal level, by detecting the minimum point of facsimile signal and making the polarity conversion signal inverting the polarity when the minimum value is smaller than the reference value. CONSTITUTION:The facsimile signal A is inputted to the terminal 1. The enphasis circuit 2 judges for the threshold value with the reference value from the signal A, performing weighting of the signal. The wave processing circuit 3 detects the minimum point of the singal B and when it is smaller than the reference value, forming the polarity conversion signal C inverting the polarity. Further, the circuit 3 delivers the facsimile signal D which is in agreement with the signal B for the level other tnan the time near the inversion of the polarity of the signal C and does not cause discontinuity for the level near the time of inversion. The circuits 5 and 6 perform multiolication for the carrier E and the signal D and the 7 is the output terminal. In the modulation circuit as this system, since no level is discontinuous even if the level is inverted every minimum point, no folding for the harmonics can be caused.

9. 发明专利

JPS5717249A LINE TERMINATOR 失效
公开(公告)号：JPS5717249A
公开(公告)日：1982-01-28
申请号：JP9164580
申请日：1980-07-07
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO
发明人： SHIMADA MASAHARU , YAMAGUCHI MASARU
IPC分类号： H04M11/06 , H04L5/22 , H04L5/24 , H04L29/02 , H04M11/00
摘要： PURPOSE:To make the type of a line terminator to one kind through the use of an interface circuit which can respectively corresponds to telephone sets, facsimile terminals and data terminals and to achive the effective use of subscriber lines through time division and multiplex of information from each terminal. CONSTITUTION:The information transmitted from telephone sets, facsimile terminals and data terminals is inputted to a terminal interface section 4 via input and output terminals 1, 2, 3. The terminal interface section 4 makes electric level conversion or logical conversion depending on the procedure of transmission control. For example, in the case of the data terminals, electric conditions of various terminals are converted into electric levels of logical ICs, and in case of a telephone set, an audio signal or a control signal is converted into a digital signal. Next, the service information and the control signal in logical conversion or electric level conversion are multiplexed at a code converter section 5. Next, multiplex signal is converted into a code waveform suitable for the lines at a level converter section 6 and transmitted to lines via a line transmission terminal 7.

10. 发明专利

JPS5717251A LINE TERMINATOR 失效
公开(公告)号：JPS5717251A
公开(公告)日：1982-01-28
申请号：JP9164780
申请日：1980-07-07
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO
发明人： SHIMADA MASAHARU , YAMAGUCHI MASARU
IPC分类号： H04M11/06 , H04L5/22 , H04L5/24 , H04L29/02 , H04M11/00
摘要： PURPOSE:To make the effective use of subscriber lines, by using an interface circuit which can respectively correspond to telephone sets, facsimile terminals and data terminals and making time division and multiplex for the information from each terminal. CONSTITUTION:Read-only memories 593, 595 produce a separation signal to separate a control information each terminal by referencing each information of a decoder 592 and the content of an index counter 550. A selector 594 outputs X to Y1 when S1 is at 1 and outputs X to YN when the output is at 1. Thus, the output of the selector 594 is separated for the control signal each terminal. Read-only memories 595, 596 are of the same functions as the read-only memories 593, 594. Thus, the service information of each output of the selector 596 is separated each terminal for output.

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