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1. 发明专利

JPH06202812A MICROCOMPUTER FOR DISK CONTROL 失效
公开(公告)号：JPH06202812A
公开(公告)日：1994-07-22
申请号：JP44793
申请日：1993-01-06
申请人： NEC CORP
发明人： MATSUSHIMA OSAMU , KATSUTA HIROSHI
IPC分类号： G06F3/06
摘要： PURPOSE:To control a disk device with the single microcomputer. CONSTITUTION:This microcomputer is provided with an instruction execution part 6 for executing servo control processing to position a head and command reception processing in response to a command S29 supplied from an external host system, A/D converter 23 connected to a head disk assembly part and the instruction execution part 6 so as to input control information required for the servo control of positioning, D/A converter 24 for outputting a servo controlled result S28 of head positioning, format control part 22 for controlling the read/write operation of serial data to the disk and the parallel data converting operation of the serial data based on the control of the instruction execution part 6, host interface part 20 for controlling the receiving operation of the command and the operation of data transfer to the external host system, and buffer control part 21 for controlling read/write operations from the format control part and an interface part to a buffer memory.

2. 发明专利

JPH06150024A MICROCOMPUTER 失效
公开(公告)号：JPH06150024A
公开(公告)日：1994-05-31
申请号：JP29942792
申请日：1992-11-10
申请人： NEC CORP
发明人： MATSUSHIMA OSAMU
IPC分类号： G06F15/78 , G06F11/26 , G06F11/273
摘要： PURPOSE:To replace an incorporated circuit group by the outside and to debug an applied system from the initial stage of design concerning the microcomputer which incorporates the circuit group to be defined by a user. CONSTITUTION:An operation mode terminal 106 is added to a microcomputer 100 and at the level of the mode terminal 106, signals required to the interface by a central processing unit(CPU) 101 and an SOG area 102 are guided to terminals 107, 108 and 109 in place of a signal line from the SOG area 102.

3. 发明专利

JPH04154221A SEQUENTIAL COMPARISON TYPE A/D CONVERTER 失效
公开(公告)号：JPH04154221A
公开(公告)日：1992-05-27
申请号：JP27825690
申请日：1990-10-17
申请人： NEC CORP
发明人： NOMA TOSHIHIRO , MATSUSHIMA OSAMU
IPC分类号： H03M1/44
摘要： PURPOSE:To simultaneously carry out a conversion operation to two analog values and to shorten the conversion time to about a half by providing a circuit generating simultaneously reference voltages having two levels by using two control registers. CONSTITUTION:This A/D converter is provided with a sampling timing generating means 16, an operational timing control means 16, a (n) voltage generating means 15, (n) comparison means 20-23, (n) sequential comparison registers 17 and 18, and a transfer means for transferring data between sequential comparison registers 17 and 18, and when a conversion result is stored in all bits of the m-th (m

4. 发明专利

JPH03242718A RESET CIRCUIT 失效
公开(公告)号：JPH03242718A
公开(公告)日：1991-10-29
申请号：JP4014790
申请日：1990-02-20
申请人： NEC CORP
发明人： NAKAMURA TAKANORI , MATSUSHIMA OSAMU
IPC分类号： G06F1/24
摘要： PURPOSE:To use the reset signal as an interrupt input by not performing the reset processing at the time of access to a RAM and preserving data in the RAM even at the time of inputting the reset signal. CONSTITUTION:When a CPU 120 indicates write to a RAM 130, a write signal the inverse of WR goes to logical value '0' and data write to the RAM 130 is started. If a reset signal IRES goes to logical value '1' during this data write, the output of a set/reset flip flop RS-FF 101 goes to logical value '1', but holding is kept in a D latch 102 because the write signal the inverse of WR of the CPU 120 is logical value '0', and the output of the D latch 102 is logical value '0' and an internal reset signal IRES is not outputted. When a write signal WR goes to logical value '1' after data write, the D latch 102 latches the output of the RS-FF 101, and the output of the D latch 102 goes to logical value '1', and the internal reset signal IRES is outputted. Thus, the reset signal can be used as an interrupt input.

5. 发明专利

JPH03130812A MICROCOMPUTER 失效
公开(公告)号：JPH03130812A
公开(公告)日：1991-06-04
申请号：JP27087089
申请日：1989-10-17
申请人： NEC CORP
发明人： MATSUSHIMA OSAMU
IPC分类号： G06F1/08 , G06F11/00 , G06F15/78
摘要： PURPOSE:To increase the operating voltage range of a microcomputer and to surely perform a shunting process of important data by switching the operating clock to another one of a low frequency when the power voltage drops and the power fail is detected. CONSTITUTION:The frequency dividers 102 and 103 are provided to produce plural driving clocks based on the output of an oscillator 101 together with a clock switch means 104 which switches selectively the dividing clocks to use them as the operating clocks of a microcomputer, and an interruption terminal 212. When a prescribed signal is inputted to the terminal 212, the means 104 is controlled. Thus the dividing clocks are changed into those of low frequencies which are used as the operating clocks of the microcomputer. Thus it is possible to increase the operating voltage range of the microcomputer at time of power fail and to surely shunt the important data.

6. 发明专利

JPH03117388A MOTOR CONTROLLER 失效
公开(公告)号：JPH03117388A
公开(公告)日：1991-05-20
申请号：JP25425689
申请日：1989-09-28
申请人： NEC CORP
发明人： ISHIMOTO TOSHIMI , MATSUSHIMA OSAMU
IPC分类号： H02P29/00
摘要： PURPOSE:To provide real-time recovery of a motor from overcurrent state and abnormal operation and to obtain a motor controller excellent in operability, general use applicability and practicality by controlling the output from a PWM signal generator based on the state of current flowing through a motor. CONSTITUTION:When a current larger than the rating current flows through a motor 4 and detected by an ammeter 5, overcurrent detection signal 9 goes to logic 1, while a PWM signal 8 goes to logic 0. Generation of the PWM signal 8 is stopped by a load signal 7 and the PWM signal 8 is fixed at logic 0 thus stopping the rotary motion of the motor 4. When the current drops below the rating current, overcurrent detection signal 7 from the ammeter 5 becomes effective and generation of the PWM signal is started with essential count at next pertod thus resuming rotary motion of the motor 4. By such arrangement, software operation can be eliminated when operation is recovered from stoppage of PWM signal due to occurrence of overcurrent or from overcurrent and thereby the processing time can be saved.

7. 发明专利

JPS62109122A INFORMATION PROCESSOR 失效
公开(公告)号：JPS62109122A
公开(公告)日：1987-05-20
申请号：JP25005685
申请日：1985-11-08
申请人： NEC CORP
发明人： MATSUSHIMA OSAMU , MAEHASHI YUKIO
IPC分类号： G06F7/00 , G06F15/78
摘要： PURPOSE:To improve greatly the processing capacity of a general-purpose register by selecting one of (p) columns through a column selecting circuit and then the data on plural m-bit registers independently among (nXm) bits through plural row selecting circuits and delivering those selected column and data to plural data buses respectively. CONSTITUTION:It is supposed that a column selection signal 2-6 is already active by a register set selecting signal 1-10 and 64 bits in the longitudinal direction of the 1st register column 2-4 are selected. Then a control gate 2-7 selects the data of total 64 bits of the register column 2-4 equivalent to eight 8-bit registers as long as the 1st reading signal 2-9 or the 2nd reading signal 2-10 is active. Then the 1st and 2nd register selecting circuits 2-13 and 2-16 select the data delivered onto the 1st and 2nd data buses 1-5 and 1-6 by the same timing and delivered again onto both buses 1-5 and 1-6 via an input/output buffer 2-14 and an output driver 2-17.

8. 发明专利

JPS6166842A Electronic control fuel injection device 失效
标题翻译：电子控制燃油喷射装置
公开(公告)号：JPS6166842A
公开(公告)日：1986-04-05
申请号：JP18865484
申请日：1984-09-07
申请人： Nec Corp
发明人： ITOKU OSAMU , MAEHASHI YUKIO , AKASHI MINEO , MATSUSHIMA OSAMU
IPC分类号： F02D41/26 , F02D41/34 , F02D45/00 , G06F19/00
CPC分类号： F02D41/26
摘要： PURPOSE:To aim at reduction in the operation process time required, by synchronizing with a process demand to be produced out of a timer part, while making time information to the timer pat and control information to a signal output part transmittable as keeping a state pertaining to program performance intact. CONSTITUTION:A timer 107 generates a process demand by the set time information after the elapse of the desired time. An output control pat 106 generates each signal controlling fuel injection timing and a fuel injection quantity in synchronous with the generation of this process demand. And, memories 113 and 114 store the processed data and programs. A central processing unit 101 performs both processes based on the process demand and the program in a selective manner. In this case, a data transmission processing device, which performs the transmission process of time information to the timer 7 and control information to the output control part 106 as keeping a state pertaining to program performance intact, should be installed in the CPU.
摘要翻译：目的：为了减少所需的操作处理时间，通过与定时器部件产生的过程需求同步，同时向定时器拍摄时间信息和控制信息，以便将信号输出部分传输为保持状态完成程序的性能。构成：定时器107在经过所需时间之后，通过设定时间信息生成处理要求。输出控制纸张106与产生该处理要求同步地产生控制燃料喷射正时和燃料喷射量的每个信号。并且，存储器113和114存储经处理的数据和程序。中央处理单元101以选择的方式基于过程需求和程序执行两个处理。在这种情况下，应该在CPU中安装向定时器7执行时间信息的发送处理和对输出控制部分106的控制信息作为保持与程序性能完好无关的状态的数据发送处理装置。

9. 发明专利

JPH0573697A MICROCOMPUTER 失效
公开(公告)号：JPH0573697A
公开(公告)日：1993-03-26
申请号：JP21971991
申请日：1991-08-30
申请人： NEC CORP
发明人： MATSUSHIMA OSAMU
IPC分类号： G06F15/78 , G06F13/42
摘要： PURPOSE:To inexpensively provide a multichannel serial interface function by operating a selection means by program processing and using the serial interface function by selectively switching it. CONSTITUTION:This system incorporates the serial interface function provided with a serial data input terminal, a serial data output terminal and a clock terminal and has a shift register 110 executing a shift-operation in synchronism with a prescribed clock signal, and a means provided with at least more than two sets of the serial data input terminal, the serial data output terminal and the clock terminal and selecting one set of them in accordance with the state of a serial channel selection flag 111. The serial interface function is selectively used by operating the serial channel selection flag 111 by program processing. Thus, the multichannel serial interface function can inexpensively be realized.

10. 发明专利

JPH03135113A A/D CONVERTER 失效
公开(公告)号：JPH03135113A
公开(公告)日：1991-06-10
申请号：JP27288889
申请日：1989-10-20
申请人： NEC CORP
发明人： MATSUSHIMA OSAMU
IPC分类号： G06F3/05 , H03M1/12
摘要： PURPOSE:To execute the conversion of an analog voltage at a high speed by starting the conversion when a storage means stores the sampling and holding of an analog voltage and stopping the conversion when the storage means is reset. CONSTITUTION:As soon as an analog voltage is held in a converter 110, it is stored that a set-reset latch 109 is set and the analog voltage is held and a logic gate 120 outputs a logical '1'. A timing control section 126 detects it to control a reference voltage generating section 125 thereby generating a reference voltage for the conversion and the converter 110 starts the conversion. An output of the converter 110 is inputted to a selector 123 and stored in a register 124-1 in the unit of one bit and when the conversion of one analog input is finished, the timing control section 126 outputs a conversion end signal 130, the set-reset latch 109 is reset, the logic gate 120 is logical '0', the timing control section 126 detects it to stop the conversion.

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