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1. 发明专利

JP2008046822A Bus controller, integrated circuit device, bus control method and program 审中-公开
标题翻译：总线控制器，集成电路设备，总线控制方法和程序
公开(公告)号：JP2008046822A
公开(公告)日：2008-02-28
申请号：JP2006221208
申请日：2006-08-14
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KUDO YOSUKE , HIGAKI NOBUO , KURATA KAZUJI , KIMURA KOZO , INOUE TAKASHI
IPC分类号： G06F13/362
摘要： PROBLEM TO BE SOLVED: To provide a bus controller for securing the processing sequence of an access request without imposing any load on a master device.
SOLUTION: This bus controller is provided with: a master queue part 11 and a slave queue part 12 in which a plurality of access requests and sequence information for determining the unique sequence between different masters of each of the access requests are stored so as to be associated with each other; a sequence control means 13 for successively selecting the plurality of access requests in the sequence to be determined by the sequence information; and access means 121X, 121Y and 121Z for issuing the plurality of access requests to one of the slave devices in the selected sequence.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于确保访问请求的处理顺序的总线控制器，而不对主设备施加任何负载。解决方案：该总线控制器设置有：主队列部分11和从队列部分12，其中存储用于确定每个访问请求的不同主机之间的唯一序列的多个访问请求和序列信息，相互关联; 一个顺序控制装置13，用于连续地选择要由序列信息确定的序列中的多个访问请求; 以及访问装置121X，121Y和121Z，用于以所选序列向一个从设备发出多个访问请求。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2005057451A Programmable logic circuit 审中-公开
标题翻译：可编程逻辑电路
公开(公告)号：JP2005057451A
公开(公告)日：2005-03-03
申请号：JP2003285468
申请日：2003-08-01
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： AOYAMA TAKAHIRO , KUDO YOSUKE
IPC分类号： H03K19/173
摘要： PROBLEM TO BE SOLVED: To provide a low-cost programmable logic circuit having a high area efficiency and for realizing a large scale and high speed logic circuit. SOLUTION: Each of a plurality of unit logic circuits is provided with a processor element 101 and a memory device 102. The processor element 101 includes a logic cell 300 the function of which can be changed on the basis of first setting information and applying prescribed logic arithmetic operation processing to an input signal to produce data and a cross connect switch 301 for carrying out arrangement, copying and inversion processing of the data from the logic arithmetic means on the basis of second setting information to generate data. Each of the plurality of unit logic circuits sequentially changes part or all of functions of the logic cell 300 and the cross connect switch 301 on the basis of the first and second setting information sequentially read from the memory device 102 and carries out operations of a prescribed sequence circuit. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供具有高面积效率和实现大规模高速逻辑电路的低成本可编程逻辑电路。解决方案：多个单元逻辑电路中的每一个设置有处理器元件101和存储器件102.处理器元件101包括逻辑单元300，其功能可以基于第一设置信息而改变，并且对输入信号应用规定的逻辑算术运算处理以产生数据，以及交叉连接开关301，用于根据第二设置信息进行来自逻辑运算装置的数据的布置，复制和反转处理，以生成数据。多个单元逻辑电路中的每一个基于从存储器件102顺序读取的第一和第二设置信息顺序地改变逻辑单元300和交叉连接开关301的一部分或全部功能，并执行规定的顺序电路。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2005229276A Programmable logic circuit 有权
标题翻译：可编程逻辑电路
公开(公告)号：JP2005229276A
公开(公告)日：2005-08-25
申请号：JP2004035043
申请日：2004-02-12
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： AOYAMA TAKAHIRO , KUDO YOSUKE
IPC分类号： H03K19/177
摘要： PROBLEM TO BE SOLVED: To provide a programmable logic circuit at a low cost with high area efficiency whereby a large-scale logic circuit can be obtained at high speed.
SOLUTION: An input output control circuit 103 gives control signals to a plurality of processor elements 101 on the basis of an input signal and gives index information to a plurality of the processor elements 101 when receiving an index instruction signal. A memory control section 201 stores a head position address denoting the head position of a storage position address of first and second setting information items in a memory device 102 on the basis of the control signal or the index information. Each of the plurality of the processor elements 101 sequentially changes part or all of their own functions on the basis of the head position address stored in the memory control section 201 and on the basis of either of the first and second setting information items sequentially read from the memory device 102 performs operations of prescribed sequence circuits.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：以低成本提供具有高面积效率的可编程逻辑电路，从而可以高速获得大规模的逻辑电路。解决方案：输入输出控制电路103基于输入信号向多个处理器元件101发出控制信号，并在接收到索引指令信号时向多个处理器元件101提供索引信息。存储器控制部分201基于控制信号或索引信息，将表示第一和第二设置信息项的存储位置地址的头位置的头位置地址存储在存储器装置102中。多个处理器单元101中的每一个基于存储在存储器控制单元201中的开头位置地址，根据顺序读取的第一设定信息项和第二设定信息项依次改变其自身功能的一部分或全部存储装置102执行规定的顺序电路的动作。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2004186815A Signal generator circuit and packet transfer apparatus 审中-公开
标题翻译：信号发生器电路和分组传输装置
公开(公告)号：JP2004186815A
公开(公告)日：2004-07-02
申请号：JP2002348749
申请日：2002-11-29
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： SUGIURA MIKITO , KUDO YOSUKE
IPC分类号： H04L12/911 , H04L12/801 , H04L12/823 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To quickly discard incoming packets at random with a variable possibility depending on the congesting condition by a small-scale circuit in a packet transfer apparatus. SOLUTION: The signal generator circuit 100 for generating a signal at a predetermined possibility decides whether incoming packets are discarded, using a signal generator circuit having a means 101 for generating random numbers, a means 102 for holding a comparison constant for comparing with the random numbers, and a means 103 for generating a signal according to the comparison result of the random numbers with the constant. COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：要解决的问题：根据分组传送装置中的小规模电路根据拥塞状况，随机地快速丢弃输入的分组。解决方案：用于以预定的可能性产生信号的信号发生器电路100使用具有用于产生随机数的装置101的信号发生器电路来确定输入分组是否被丢弃，用于保持比较常数的装置102用于与随机数，以及根据随机数与常数的比较结果产生信号的装置103。版权所有（C）2004，JPO＆NCIPI

5. 发明专利

JP2005229275A Programmable logic circuit 有权
标题翻译：可编程逻辑电路
公开(公告)号：JP2005229275A
公开(公告)日：2005-08-25
申请号：JP2004035042
申请日：2004-02-12
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： AOYAMA TAKAHIRO , KUDO YOSUKE
IPC分类号： H03K19/177
摘要： PROBLEM TO BE SOLVED: To provide a programmable logic circuit at a low cost with high area efficiency whereby a large-scale logic circuit can be obtained at high speed. SOLUTION: A processor element 101 includes: a logic cell 300 the function of which can be revised on the basis of first setting information and for applying prescribed logic arithmetic processing to an input signal to generate data; a cross-connect switch 301 for applying arrangement, copying and inversion processing to the data from the logic arithmetic means on the basis of second setting information to generate data; and a memory control section 201 for reading either of the first and second setting information items in a memory device 102 and giving the read information to the logic arithmetic means and a data processing means to control them. Each of a plurality of unit logic circuits sequentially changes part or all of the functions of the logic cell 300 and the cross-connect switch 301 to perform operations of prescribed sequence circuits on the basis of the first and second setting information items sequentially read from the memory device 102. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：以低成本提供具有高面积效率的可编程逻辑电路，从而可以高速获得大规模的逻辑电路。解决方案：处理器元件101包括：逻辑单元300，其功能可以基于第一设置信息进行修改，并且用于对输入信号应用规定的逻辑运算处理以生成数据; 交叉连接开关301，用于基于第二设置信息对来自逻辑运算装置的数据进行布置，复制和反转处理，以生成数据; 以及存储器控制部分201，用于读取存储器件102中的第一和第二设置信息项中的任一个，并将读取的信息提供给逻辑运算装置，以及数据处理装置来控制它们。多个单位逻辑电路中的每一个顺序地改变逻辑单元300和交叉连接开关301的功能的一部分或全部，以根据从第一和第二设置信息项顺序读取的第一和第二设置信息项执行规定的顺序电路的操作存储装置102.版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2005057452A Programmable logic circuit 审中-公开
标题翻译：可编程逻辑电路
公开(公告)号：JP2005057452A
公开(公告)日：2005-03-03
申请号：JP2003285469
申请日：2003-08-01
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： AOYAMA TAKAHIRO , KUDO YOSUKE
IPC分类号： H03K19/173
摘要： PROBLEM TO BE SOLVED: To provide a programmable logic circuit at a low cost having a high area efficiency and realizing a high speed large scale logic circuit.
SOLUTION: A processor element 101 includes: a logic cell 300 for carrying out prescribed logic arithmetic processing to generate data; a cross connect switch 301 for carrying out arrangement, copying and inversion processing of the data from the logic arithmetic means on the basis of second setting information to generate data, and a selection unit 302. Each of a plurality of unit logic circuits sequentially changes part or all of functions of the logic cell 300 and the cross connect switch 301 on the basis of the first and second setting information sequentially read from the memory device 102 and carries out operations of a prescribed sequence circuit. The selection unit 302 stores the data from the cross connect switch 301, selects any of the stored data on the basis of third setting information and provides an output of the selected data.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供具有高面积效率的低成本的可编程逻辑电路，并实现高速大规模逻辑电路。解决方案：处理器元件101包括：逻辑单元300，用于执行规定的逻辑运算处理以产生数据; 交叉连接开关301，用于根据第二设置信息进行逻辑运算装置的数据的布置，复制和反转处理以产生数据;以及选择单元302.多个单元逻辑电路中的每一个顺序地改变部分或逻辑单元300和交叉连接开关301的功能，或者从存储装置102顺序读取的第一和第二设定信息，进行规定的顺序电路的动作。选择单元302存储来自交叉连接开关301的数据，基于第三设置信息选择任何存储的数据，并提供所选数据的输出。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2002300121A OPTICAL NETWORK UNIT 失效
公开(公告)号：JP2002300121A
公开(公告)日：2002-10-11
申请号：JP2001100286
申请日：2001-03-30
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： KUDO YOSUKE , NAGATA TAKESHI , YATABE HIDEAKI
IPC分类号： G01M11/00 , H04B10/00 , H04B10/077 , H04B10/079 , H04B17/00 , H04B10/22
摘要： PROBLEM TO BE SOLVED: To economically and simply conduct adjustment and inspection of an optical module without the need for using an expensive exclusive measure ment instrument such as a multi-channel generator by providing a clock generat ing section generating a test pattern in an optical subscriber line terminating unit (ONU). SOLUTION: A CPU section 15 in an Ether/PDS-LSI 10 instructs a conversion circuit 15 for the operation in the optical module adjustment mode on the basis of an optical module adjustment mode command received from an adjustment inspection PC 24. The conversion circuit 16 generates a test pattern and a clock used for adjustment and inspection of an optical module section (LD/PD) 3 and supplies them to a test mode circuit 11. Thus, a laser diode in the optical module section 3 is driven via an analog IC interface circuit 12 and an analog IC 2 and an optical signal corresponding to the test pattern is transmitted. The test pattern to be generated can be selected on the basis of pattern designation data.

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