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1. 发明专利

JP2001267557A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2001267557A
公开(公告)日：2001-09-28
申请号：JP2000071151
申请日：2000-03-14
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： EZAKI TAKEYA
IPC分类号： H01L21/28 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8234 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a fine semiconductor device corresponding to reduction of gate length, and to provide its manufacturing method. SOLUTION: A sidewall insulating film 6 is formed on a side surface of an embedded gate electrode 3 on an Si substrate 1. A trench-type insulating film 10 for element isolation, which is formed through self alignment to the embedded gate electrode 3, is arranged up to a position higher than the embedded gate electrode 3. A source/drain contact 13, which makes contact with a high concentration source/drain diffusion region 12, is formed between the sidewall insulating film 6 and the insulating film 10. Since the source/drain contact 13 and the insulating film 10 are formed in a self-alignment manner to the embedded gate electrode 3, margin for mask alignment becomes unnecessary, and the whole active region or the dimension in the gate length direction of the source/drain contact 13 and the high concentration source/drain region 12 can be reduced.

2. 发明专利

JPH0465530B2 失效
公开(公告)号：JPH0465530B2
公开(公告)日：1992-10-20
申请号：JP20610190
申请日：1990-08-02
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： EZAKI TAKEYA , ISHIKAWA OONORI
IPC分类号： H01L21/336 , H01L29/78

3. 发明专利

JPH03129741A MANUFACTURE OF MOS-TYPE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH03129741A
公开(公告)日：1991-06-03
申请号：JP20610090
申请日：1990-08-02
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： EZAKI TAKEYA , ISHIKAWA ONORI
IPC分类号： H01L21/336 , H01L29/78
摘要： PURPOSE:To accurately control a spread of a diffusion layer into a part directly under a gate and to form an effective channel length of high accuracy by a method wherein an insulating film with which a side face of the gate is covered is left as an insulating-film pattern, impurities are introduced into the surface of a substrate by making use of the gate and the insulating-film pattern as a mask and a source and a drain are formed. CONSTITUTION:A field oxide film 2 and a gate oxide film 3 are formed in desired positions of a silicon substrate. A polycrystalline silicon film 4 is deposited on them; a photoresist pattern 5 used to form a gate pattern is formed. The polycrystalline silicon film 4 is etched by making use of the photoresist pattern 5 as a mask. A silicon oxide film 6 is deposited on it. Then, an etching gas 50 is made incident nearly perpendicularly to the surface of the substrate 1; the oxide film 6 is removed selectively. After that, phosphorus or arsenic is introduced by making use of a gate 4' and an insulating-film pattern 6' as a mask; a source diffusion layer and a drain diffusion layer 7, 8 are formed. At this time, a junction depth is adjusted in such a way the a spread in a transverse direction of the diffusion layers 7 and 8 becomes larger than a width W of the oxide film pattern 6'.

4. 发明专利

JPH0363736A SEMICONDUCTOR PROCESS DATA ACCUMULATION SYSTEM 失效
公开(公告)号：JPH0363736A
公开(公告)日：1991-03-19
申请号：JP19897189
申请日：1989-07-31
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： SAWADA AKIHIRO , MATSUMOTO SHIGERU , EZAKI TAKEYA
IPC分类号： G06F12/00 , H01L21/66
摘要： PURPOSE:To prevent the capacity of a file from being increased by increasing the number of wafers by collecting wafer numbers, which are processing under the same condition, into an wafer number storage item by an wafer number sectioned by a comma or the arbitrarily same character. CONSTITUTION:A means 1 is provided to register and accumulate a rot name, process name, process condition value and wafer number to a lot history information data base as an item value in an order, with which the lot is really processed, for each same process condition value at least. Then, a means 2 is provided to extract the two adjacent records from the lot history information data base, and a means 3 is provided to compare the item values between the two extracted records. Further, a means 4 is provided to prepare a compressed lot history data base equipped with an wafer number storage item together with the item excepting for wafer number storage, namely, with the lot name, process name and process condition value. Thus, the plural wafer numbers processed under the same condition can be written into the wafer number storage item and the information of the wafer numbers processed under the same condition can be defined as one record.

5. 发明专利

JPH02203566A MOS TYPE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02203566A
公开(公告)日：1990-08-13
申请号：JP2419189
申请日：1989-02-02
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： EZAKI TAKEYA
IPC分类号： H01L29/78
摘要： PURPOSE:To make impurity concentration sharp and dilute by forming in order a punch through protecting layer of sharp distribution and a punch through protecting layer of gentle distribution so as to be in contact with the lower part of a burried layer. CONSTITUTION:In the vicinity containing the surface of an n-type semiconductor substrate 1, a polycrystalline silicon gate 3 is formed, via a p-type buried layer 7 having a specified concentration and thickness, and a gate oxide film 2 formed on the substrate 1 surface. On both ends of the gate 3, a p-type source 4 and a drain 5 of high concentration formed by implanting boron are formed as diffusion layers. A punch through protecting layer 61 of sharp distribution and a punch through protecting layer 62 of gentle and low concentration formed in order so as to be in contact with the lower part of the buried layer 7 are arranged. Thus a p-channel MOSFET is constituted. A part of the lower part of the buried layer 7 is compensated by the protecting layers 61, 62, and inverted into one conductivity type, so that the distribution of the buried channel becomes sharp.

6. 发明专利

JPH0245950A BURNOUT DETECTION METHOD 失效
公开(公告)号：JPH0245950A
公开(公告)日：1990-02-15
申请号：JP19742088
申请日：1988-08-08
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： URAOKA KOUJI , NAKADA YOSHIRO , EZAKI TAKEYA
IPC分类号： H01L21/66
摘要： PURPOSE:To detect burnout by adding electric field between either terminal end of a wiring body and a substrate and monitoring light radiated from the semiconductor/insulation film interface at a part which electric field is applied to. CONSTITUTION:If burnout occurs in a wiring body 40 on a semiconductor substrate 30 provided through an insulation film 20, electric field occurs due to a power supply 50 between the wiring body 40 and the substrate 30. Emission occurs between the insulation film 20 and the substrate 30. However, since no electric field is generated at an area to the right of a burnout point 45, no light is emitted from the interface below it. Thus, by monitoring emission, burnout from that interface can be detected.

7. 发明专利

JPH01110737A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01110737A
公开(公告)日：1989-04-27
申请号：JP26855587
申请日：1987-10-23
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MORII TOMOYUKI , EZAKI TAKEYA
IPC分类号： H01L29/78 , H01L21/318 , H01L21/336
摘要： PURPOSE:To manufacture a semiconductor device provided with a more stable passivation film by a method wherein an Si3N4 film deposited on a gate by pressure reduced CVD process and another Si3N4 film (passivation film) deposited on the Si3N4 film by plasma CVD process are provided on a conductivity type semiconductor substrate. CONSTITUTION:An Si3N4 film 6 deposited on a gate by pressure reduced CVD process is provided on a conductivity type semiconductor substrate 1 through the intermediary of a gate insulating film 2 and then another Si3N4 film (passivation film) 7 deposited on the Si3N4 film 6 by plasma CVD process is provided. For example, the LP-Si3N4 film 6 is deposited by pressure reduced process leaving a protective oxide film 5 in case of forming an n type diffused layer 4 around a polysilicon gate 3 provided on the p conductivity type semiconductor substrate 1 through the intermediary of the gate oxide film 2 and then the p-Si3N4 film 7 is deposited by plasma CVD process as a passivation film. Through these procedures, hydrogen ion 8 in the p-Si3N4 film 7 can be prevented from permeating into the gate oxide film 2 or the interface between the gate oxide film 2 and the semiconductor substrate 1.

8. 发明专利

JPS6437851A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6437851A
公开(公告)日：1989-02-08
申请号：JP19467687
申请日：1987-08-04
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： URAOKA KOUJI , EZAKI TAKEYA
IPC分类号： H01L23/52 , H01L21/3205
摘要： PURPOSE:To form a stabilized wiring by thinly depositing a chemically stable high melting-point metal or an silicide thereof immediately after Al is deposited and protecting Al from damage such as dry etching when the Al metallic wiring is shaped. CONSTITUTION:A high melting-point silicide 2 such as Tasix is deposited thinly immediately after an n layer (n=1, 2...) Al wiring 1 is deposited in specified thickness. A resist 4 is applied and a pattern is formed through a photoetching process. Dry etching is conducted, using the resist as a mask. When a device is damaged when a metallic pattern is shaped through the dry etching, the resist 4 is removed, and the surface or the whole of the patterned silicide 2 is gotten rid of by hydrofluoric acid. An insulating film is deposited. An inter- layer film 5 is etched in order to bore a through-hole 5a, and the surface of the silicide 2 is etched chemically, thus taking off damage.

9. 发明专利

JPS6425474A MANUFACTURE OF MOS TYPE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6425474A
公开(公告)日：1989-01-27
申请号：JP18148987
申请日：1987-07-21
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MATSUMOTO SHIGERU , EZAKI TAKEYA
IPC分类号： H01L27/088 , H01L21/8234 , H01L27/08 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/78
摘要： PURPOSE:To reduce the wiring resistance of a gate and to improve gate oxide film characteristics by forming a main gate pattern by etching, reproducing a gate oxide film by thermal oxidizaition, then forming a sidewall gate on the side of a main gate, and forming a high concentration source, drain by ion implantation. CONSTITUTION:A polysilicon 3 is deposited through a gate oxide film 2 on a P-type Si substrate 1, and an etching mask oxide film 4 for forming a gate pattern is formed. When the thickness of the polysilicon part 32 becomes half of the initial one, the etching is stopped, and a silicon nitride film 5 is formed on the side face of the polysilicon 31 covered with a mask 4. Then, the polysilicon 32 is again etched to form a main gate 31 of the polysilicon, and thermally oxidized. Then, after the silicon nitride film is removed with thermal phosphoric acid solution, a TiSix thin film 8 is formed at the sidewall of the gate 31, with it as a mask arsenic 6 is ion implanted in high concentration to form an N type region 7.

10. 发明专利

JPS63227033A DETECTING METHOD FOR MASK ALIGNMENT DEVIATION OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63227033A
公开(公告)日：1988-09-21
申请号：JP6155587
申请日：1987-03-17
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： EZAKI TAKEYA
IPC分类号： H01L21/66 , H01L21/027 , H01L21/30 , H01L21/68
摘要： PURPOSE:To simply and accurately obtain a mask displacement by directly measuring the displacement by a potential difference. CONSTITUTION:A square-shaped bridge is composed of 4 resistors R1-R4 which vary their resistance values by mask alignment deviation, the resistors arranged at opposite sides are so disposed as to similarly vary by the deviation, an external voltage is applied between two opposite connecting points of 4 connecting points 3, 5, 4a, 4b among 4 resistors R1-R4, and a potential difference between the other pair is measured. The potential difference DELTAV at the intermediate point of the bridge is measured to detect a mask displacement, and the measured potential DELTAV is directly proportional to the mask displacement DELTAW. Thus, the mask displacement can be simply and accurately electrically detected.

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