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1. 发明专利

JPH1021658A DIGITAL AURAL SIGNAL REPRODUCING DEVICE 失效
公开(公告)号：JPH1021658A
公开(公告)日：1998-01-23
申请号：JP17697496
申请日：1996-07-08
申请人： MITSUBISHI ELECTRIC CORP , MATSUSHITA ELECTRIC IND CO LTD
发明人： KUMANO MAKOTO , NANBA TAKAHIRO , INOUE HARUHISA , ISHIWATARI TETSUO , OKA HIDEMI , ISHIMOTO SHUNEI
IPC分类号： G11B20/10 , G11B20/18
摘要： PROBLEM TO BE SOLVED: To set mute conditions flexibly and to prevent a noise generated at a mode changing point. SOLUTION: Assuming that one frame of delay is produced when a reproducing discrimination signal is transmitted from a demultiplexer 11 to a control part 14, and one frame of delay is produced when an operation mode instruction is transmitted from the control part 14 to a decoder 12 and coincidence detecting circuit 15, the timing of operation instruction mode is delayed by two frames from the reproducing identifying signal. The coincidence detecting circuit 15 compares the reproducing discrimination signal and the operation mode instruction. For that purpose, in a period that states of the reproducing discrimination signal and the operation mode instruction are different, a second mute control signal is activated to make it possible to prevent noise generated in a mute part 13.

2. 发明专利

JPH08223527A TIME SERIES DATA PROCESSOR 失效
公开(公告)号：JPH08223527A
公开(公告)日：1996-08-30
申请号：JP2207495
申请日：1995-02-09
申请人： MITSUBISHI ELECTRIC CORP , MATSUSHITA ELECTRIC IND CO LTD
发明人： KUMANO MAKOTO , NANBA TAKAHIRO , INOUE HARUHISA , ISHIWATARI TETSUO , ISHIMOTO SHUNEI , OKA HIDEMI
IPC分类号： H04N5/91 , G11B20/14 , H03M9/00 , H04N5/92 , H04N5/93
摘要： PURPOSE: To simplify a circuit configuration by selecting and synthesizing input audio data of four channels through bit processing and outputting to a desired output channel. CONSTITUTION: A parallel serial converter 1 converts input voice data 10 of four channels in 16-bit per channel into serial data in 1 bit, which are outputted to a data bus 111 and a 16-stage shift register 21 via a signal line 100. Each of 16-stage shift registers 21, 22, 23 is made up of 16 sets of D flip-flop circuits in cascade connection, for example, and delays data in 16-bit and outputs the resulting data to a data bus 111 in 4-bit width via signal lines 210, 220, 230. Under the control of an audio selection control section 8, 4-1 selectors 31, 32, 33, 34 select alternatively 4-bit data in a timing of time series data and outputs the data to signal lines 310, 320, 330, 340. Thus, the signals of the selected input channel are obtained on a desired signal line alternately.

3. 发明专利

JPH08223000A CLOCK GENERATION CIRCUIT 失效
公开(公告)号：JPH08223000A
公开(公告)日：1996-08-30
申请号：JP2207395
申请日：1995-02-09
申请人： MITSUBISHI ELECTRIC CORP , MATSUSHITA ELECTRIC IND CO LTD
发明人： NANBA TAKAHIRO , KUMANO MAKOTO , INOUE HARUHISA , YOSHINO TADASHI , ISHIWATARI TETSUO , OKA HIDEMI
IPC分类号： G06F1/06 , H03B19/00 , H03K3/02
摘要： PURPOSE: To obtain a clock signal with a frequency required with a few oscillating elements by providing the oscillation elements generating clock signals of prescribed frequencies, a frequency divider frequency-dividing a reference clock signal by a prescribed division ratio, a delay circuit delaying the clock signal by a prescribed clock time, and an exclusive logic circuit between outputs from the frequency divider and the delay device. CONSTITUTION: A reference clock 40 whose frequency is 24.576MHz (48k×512MHz) generated by a reference clock signal generating circuit 41 is frequency-divided by 1/2 (n=1) by a 1/2n frequency divider 26 to generate a master clock 256fs (48k×256MHz) with respect to a sampling frequency fs =48kHz. Furthermore, the clock signal 40 is frequency-divided by 1/6 with a 1/6n frequency divider 27 and an output clock A from the frequency divider 27 is given to a DFF circuit 29 and an EXOR circuit 31. On the other hand, an output clock obtained by applying 1/n frequency division to the clock signal 40 at a 1/n frequency divider 28 is inverted by a circuit 33 and the inverted clock signal is given to DFF29, 30, and a clock B delayed from the clock signal subject to 1/n frequency division by 0.5 clock signal time is outputted from a FF 29. The clock B is given to a circuit 30, from which a clock C delayed by 1/4 clock signal time is given to a circuit 31, from which a master clock signal whose frequency is 32k×256MHz is outputted.

4. 发明专利

JPH08212051A SERIAL DATA INTERFACE DEVICE 失效
公开(公告)号：JPH08212051A
公开(公告)日：1996-08-20
申请号：JP2059595
申请日：1995-02-08
申请人： MITSUBISHI ELECTRIC CORP , MATSUSHITA ELECTRIC IND CO LTD
发明人： INOUE HARUHISA , KUMANO MAKOTO , NANBA TAKAHIRO , YOSHINO TADASHI , ISHIMOTO SHUNEI , OKA HIDEMI
IPC分类号： G06F3/16 , G06F5/00
摘要： PURPOSE: To sharply reduce the size of a circuit in a serial data interface device for inputting/outputting serial data defining (m) bits as one word. CONSTITUTION: In the serial data interface device for inputting sound serial data of defining sixteen bits as one word, a data phase control circuit 203 outputs sound serial data with a fixed format from an output of a shift register 6 based upon a timing signal obtained by referring to an input serial data mode signal and a bit position signal outputted from a bit position generator 300 independently of the format of inputted serial data.

5. 发明专利

JP2007074634A Moving image compressing apparatus 有权
标题翻译：移动图像压缩装置
公开(公告)号：JP2007074634A
公开(公告)日：2007-03-22
申请号：JP2005262002
申请日：2005-09-09
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： FUJII SHOZO , OKA HIDEMI , MIZUNO SHINJIRO , SETO SHINYA , ARIMURA KOJI
IPC分类号： H03M7/30 , H04N19/124 , H04N19/13 , H04N19/134 , H04N19/14 , H04N19/196 , H04N19/423 , H04N19/50 , H04N19/51
摘要： PROBLEM TO BE SOLVED: To prevent occurrence of image quality deterioration by preventing response from being delayed even when a state of an input video image is changed in a VBR type moving image compressing apparatus. SOLUTION: A moving image compressing apparatus comprises: a video information detection means 3 for determining video information by comparing an encoded screen from an encoded screen memory 1 with a reference screen from a reference screen memory 2; a compression state predicting means 5 for calculating compression prediction information α from a degree of a change between video information in the past and video information of the encoded screen; and a code amount control means 6 for determining a code amount to be assigned to the encoded screen using a code amount based on encoding in the past, a result value of a quantization index and the compression prediction information α. Thus, a difficulty level of compression is relatively determined from the degree of the change in the video information and the determined difficulty level is operated upon the code amount and the result value of the quantization index as compression prediction information to determine accurate code amount assignment. As a result, high image quality can be achieved at all the time without delaying code amount control from a video image change. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：即使当在VBR型运动图像压缩装置中改变输入视频图像的状态时，通过防止响应延迟来防止图像质量劣化的发生。运动图像压缩装置包括：视频信息检测装置3，用于通过将来自编码屏幕存储器1的编码屏幕与参考屏幕存储器2的参考屏幕进行比较来确定视频信息; 压缩状态预测装置5，用于从过去的视频信息和编码的屏幕的视频信息之间的变化程度计算压缩预测信息α; 以及代码量控制装置6，用于使用基于过去的编码的代码量，量化索引的结果值和压缩预测信息α来确定要分配给编码屏幕的代码量。因此，根据视频信息的变化程度相对地确定压缩的难度级别，并且将所确定的难度级别作为压缩预测信息，将代码量和量化索引的结果值进行操作，以确定准确的代码量分配。结果，可以始终实现高图像质量，而不会延迟视频图像改变的代码量控制。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2002305748A VARIABLE LENGTH CODING METHOD, VIDEO COMPRESSION METHOD AND DEVICE EMPLOYING THEM 失效
公开(公告)号：JP2002305748A
公开(公告)日：2002-10-18
申请号：JP2001105449
申请日：2001-04-04
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： FUJII SHOZO , OKA HIDEMI , MIZUNO SHINJIRO
IPC分类号： H04N19/50 , H03M7/30 , H03M7/40 , H04N19/42 , H04N19/46 , H04N19/463 , H04N19/503 , H04N19/51 , H04N19/513 , H04N19/52 , H04N19/60 , H04N19/61 , H04N19/625 , H04N19/68 , H04N19/70 , H04N19/91 , H04N7/32 , H04N7/30
摘要： PROBLEM TO BE SOLVED: To solve a problem of a conventional device compatible with both the DV (Specification of Consumer-Use Digital VCRs Using 6.3 mm Magnetic Tape) compression and the compression utilizing other inter-frame correlation such as the MPEG that has needed a large circuit scale, has been expensive and has required high power consumption because respective companders are to be independently installed. SOLUTION: A variable length code in matching with the definition of a code word of the variable length code in compliance with the DV standard is adopted for variable length coding of a compressor employing inter-frame correlation. The device is provided with an exception processing section 5 that conducts exception processing of coding the code word of variable length coding into predetermined other code word when the code word resulting in variable length coding takes a particular bit pattern (especially all bits become '1') and also has a configuration of attaching adjacent difference information of a motion vector or motion vectors to a series of coefficients after orthogonal transform to apply variable length coding to the resulting coefficients.

7. 发明专利

JP2002112191A VIDEO RECORDER, MEDIUM AND INFORMATION AGGREGATE 失效
公开(公告)号：JP2002112191A
公开(公告)日：2002-04-12
申请号：JP2000298589
申请日：2000-09-29
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： YOSHINO TADASHI , OKABE MASAO , OKA HIDEMI , YOSHIDA KATSUHIKO , MIZUNO SHINJIRO
IPC分类号： H04N5/7826 , G11B20/10 , H04N5/92
摘要： PROBLEM TO BE SOLVED: To solve a problem of the conventional consumer digital video tape recorders, adopting the technology of the existing professional digital VTR system as it is, can ensure only a recording time of 30 minutes for a small cassette, when recording a 480/60p signal that is a half of 60 minutes, when recording a 480/60i signal and likewise only a recording time of 15 minutes, when recording a 720/60p signal. SOLUTION: When recording 480/60p signal to the 720/60p signal, a high compression rate of a video signal is adopted to reduce a video data quantity through compression, and a high digital modulation frequency is employed to record the resulting video data onto a magnetic tape, so as to ensure a recording time of 60 minutes for the small cassette, when recording the 480/60p signal and the recording time of 30 minutes for the small cassette, when recording the 720/60p signal.

8. 发明专利

JP2001008156A IMAGE RECORDING AND REPRODUCING DEVICE 失效
公开(公告)号：JP2001008156A
公开(公告)日：2001-01-12
申请号：JP17357399
申请日：1999-06-21
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： YOSHIDA KATSUHIKO , OKABE MASAO , MIZUNO SHINJIRO , OKA HIDEMI
IPC分类号： H04N5/91 , G11B27/28
摘要： PROBLEM TO BE SOLVED: To efficiently record still images and to easily execute access to the recorded still images and their management by solving problems that the number of pictures allowed to be recorded is sharply reduced when the same still image is repeatedly recorded in a magnetic tape over 6 to 7 sec and much time is required for accessing a required still image. SOLUTION: A counting means 115 outputs the number of still images continuously recorded in a magnetic tape 101 as a count value, an index preparation circuit 111 prepares an index image by repeating the compression of a still image to be recorded to 1/n data volume in each updating of the count value and the storage of the compressed image in a position corresponding to the count value in an index image memory 112 and a controller 105 records an index image on a tape position continued to m still images which have been already recorded in a recording signal processing circuit 114 when the count value becomes (m).

9. 发明专利

JP2000165841A DATA TRANSMITTER-RECEIVER 失效
公开(公告)号：JP2000165841A
公开(公告)日：2000-06-16
申请号：JP33716798
申请日：1998-11-27
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： KAWAKAMI KAZUO , OKA HIDEMI
IPC分类号： H04N5/91 , G06F21/10 , G11B20/10 , H04N5/92 , H04N7/167 , H04N19/00 , H04N19/42 , H04N19/423 , H04N19/467 , H04N21/4367 , H04N21/4408 , H04N21/442 , H04N7/24
摘要： PROBLEM TO BE SOLVED: To provide a data transmitter-receiver by which data processing for encryption and decoding is selected with a simple configuration by discriminating a type of video compression data. SOLUTION: Digital data are encrypted or decoded by using an encryption key generated by an authentication section 3 depending on a capacity predetermined on the basis of video compression by digital video DV or moving picture experts group MPEG or the like discriminated by a video compression discrimination section 5, and a processing procedure of the digital data among a storage section 6 such as a memory or FIFO, an encryption section 7 and a decoding section 8 is selected based on video compression information by the video compression discrimination section 5 go as to have provision for encryption on the IEEE 1394 and to separate the data into the data depending on the video compression such as the DV or MPEG.

10. 发明专利

JPH09130745A VIDEO SIGNAL RECORDER 失效
公开(公告)号：JPH09130745A
公开(公告)日：1997-05-16
申请号：JP28478295
申请日：1995-11-01
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： YAMAMOTO YOSHINORI , KASHIRO TAKAO , YAMAUCHI EIJI , OKA HIDEMI
IPC分类号： H04N5/91 , H04N5/92
摘要： PROBLEM TO BE SOLVED: To record a video signal so as to avoid a reproduced image from swinging vertically even when an input video signal with discontinuous fields is recorded. SOLUTION: A vertical synchronizing signal of an input video signal is detected (102) and a frame reference signal is generated (103). In this case, the video signal is recorded so as to avoid an image from swinging at reproduction by selecting different phase from rising and falling of the frame reference signal with respect to the vertical synchronizing signal part of the video signal.

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