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    • 1. 发明专利
    • Frequency modulator, frequency modulation method, and radio circuit device
    • 频率调制器,频率调制方法和无线电电路设备
    • JP2003273651A
    • 2003-09-26
    • JP2002066884
    • 2002-03-12
    • Matsushita Electric Ind Co Ltd松下電器産業株式会社
    • ADACHI HISASHISAKAKURA MAKOTO
    • H03M7/32H03C3/00H03C3/04H03C3/09H03L7/197H03M7/00H04L27/12
    • H03C3/0966H03C3/0925H03C3/0933H03C3/0941H03C3/095H03C3/0958H03L7/1976H03M7/3022H03M7/3037H03M7/304H04L27/12
    • PROBLEM TO BE SOLVED: To provide a frequency modulator with which a reference signal source having no frequency modulation function can be used and wide band modulation is performed on the basis of a digital modulation signal. SOLUTION: A phase-locked loop (PLL) is formed from a voltage controlled oscillator 1, a variable frequency divider 2, a phase comparator 3, and a loop filter 4. A sigma/delta modulator 5 applies sigma/delta modulation to data obtained by adding fractional data M2 and modulation data X with the output signal of the variable frequency divider 2 as a clock. The output signal of the sigma/delta modulator 5 is added with integral data M1 and becomes effective frequency division data 13 of the variable frequency divider 2. At the same time, the output signal of the sigma/delta modulator 5 is passed through a D/A converter 6, a low-pass filter 7, and an amplitude control circuit 8 and becomes a control signal 14. The control signal 14 is inputted to the frequency modulation terminal of the voltage controlled oscillator 1. COPYRIGHT: (C)2003,JPO
    • 要解决的问题:提供一种可以使用不具有频率调制功能的参考信号源的频率调制器,并且基于数字调制信号进行宽带调制。 解决方案:锁相环(PLL)由压控振荡器1,可变分频器2,相位比较器3和环路滤波器4形成。Σ/Δ调制器5应用Σ/Δ调制 通过将分数数据M2和调制数据X与可变分频器2的输出信号相加而获得的数据作为时钟。 Σ/Δ调制器5的输出信号加上积分数据M1,成为可变分频器2的有效分频数据13.同时,Σ/Δ调制器5的输出信号通过D / A转换器6,低通滤波器7和振幅控制电路8,并成为控制信号14.控制信号14被输入到压控振荡器1的调频端。 )2003,JPO
    • 5. 发明专利
    • PLL CIRCUIT
    • JP2000332602A
    • 2000-11-30
    • JP14058599
    • 1999-05-20
    • MATSUSHITA ELECTRIC IND CO LTD
    • YOKONAGA HIROYUKISAKAKURA MAKOTOANDO TOSHIAKIISHIDA KAORU
    • H03L7/08H03B5/12H03L7/093H03L7/099
    • PROBLEM TO BE SOLVED: To cancel fluctuation to ground or a power source and influences of noise from electromagnetic field interference from an antenna by equipping a voltage control oscillator for oscillation outputting a differential voltage signal and a frequency divider for frequency dividing the differential output signal of the voltage control oscillator and outputting it as another signal of a phase comparator. SOLUTION: In a voltage control oscillator 5, an oscillation frequency is controlled by a potential difference between an SLPF1 and an SLPF2 of output signals of a loop filter 4, output signals fvco1 and fvco2 are differentially outputted and its output differential voltage signal is inputted to a frequency divider 6. The frequency divider 6 inputs the differential voltage signals thus inputted to a phase comparator 2 as output signals by frequency dividing them into voltage signals fc. In this way, since all the voltage signal paths are received and delivered with the differential voltage signals, it is possible to cancel influences of noise accompanying potential change of a ground or a power source and noise of the same phase to electromagnetic field interference by a radiation electromagnetic wave of an antenna.
    • 10. 发明专利
    • HIGH FREQUENCY CIRCUIT DEVICE
    • JPH02107001A
    • 1990-04-19
    • JP26081288
    • 1988-10-17
    • MATSUSHITA ELECTRIC IND CO LTD
    • SAKAKURA MAKOTOOGAWA KOICHIHASHIMOTO KOJI
    • H01P3/08H01P5/08
    • PURPOSE:To reduce a parasitic impedance caused by a lead line by providing a semiconductor chip, of which the electrode is mounted so as to be exactly or approximately on the same plane as the electrode part of a ground conductor, at the recessed part of the ground conductor. CONSTITUTION:A pedestal 3a of the ground conductor has the recessed part, which is provided so that the top-face electrode parts of the pedestal 3a and an FET chip 4 may be the same or approximately the same plane. Consequently, the length of a bonding wire 7 to connect between the source electrode part of the FET chip 4 and the electrode part of the pedestal 3a can be reduced. When the height dimension of the drain/gate electrode part of the FET chip 4 is the same or approximately the same as the height dimension of a microstrip line 6 of input/output side dielectric substrates 2a and 2b, the length of the bonding wire 7 to connect between them can be made shorter. Thus, the parasitic impedance caused by the lead line can be suppressed to a small value, and the stable high frequency characteristic can be obtained.