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1. 发明专利

JP2005301476A Power supply control system and storage device 审中-公开
标题翻译：电源控制系统和存储设备
公开(公告)号：JP2005301476A
公开(公告)日：2005-10-27
申请号：JP2004113829
申请日：2004-04-08
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SASAKURA TAKAHIRO , ABE SEIICHI
IPC分类号： G06F1/28 , G01R31/30 , G01R31/317 , G05F1/00 , G05F1/10 , G06F1/20 , G06F1/26 , G06F1/30 , G06F3/06 , G06F11/00 , G06F11/20
CPC分类号： G06F1/26 , G01R31/3004 , G01R31/31721 , G06F1/206 , G06F11/2015 , Y10T307/50
摘要： PROBLEM TO BE SOLVED: To analyze the failure of the power source circuit part by storing the fluctuation history of voltage data before the power source circuit part is put into an abnormal state, when the power source circuit part is put into the abnormal state. SOLUTION: An arithmetic processing part controls a hot swap circuit 17, and DC/DC converters 3 to 13 on the basis of binary data from an ADC 25 and an interrupting signal in a predetermined logical level from each comparing part of a voltage detecting circuit 15. When the interruption signal in the predetermined logical level is inputted from any comparing part, reading of the binary data corresponding to the interruption signal is stopped. The binary data which are stored in an SRAM at that point of time and are related to the voltage detecting part corresponding to the interruption signal, are transferred to a non-volatile memory 23 so as to be stored. After the driving of this system stops, the binary data for analyzing the factor of abnormality are read from the non-volatile memory 23, and the cause of abnormality of the DC/DC converter whose output voltage shows abnormality is analyzed. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了通过在电源电路部分处于异常状态之前存储电压数据的波动历史来分析电源电路部分的故障，当电源电路部分进入异常状态时州。解决方案：算术处理部分基于来自ADC 25的二进制数据和来自电压的每个比较部分的预定逻辑电平的中断信号来控制热插拔电路17和DC / DC转换器3至13 检测电路15.当从任何比较部分输入预定逻辑电平的中断信号时，停止与中断信号对应的二进制数据的读取。存储在该时刻的SRAM中并且与对应于中断信号的电压检测部相关的二进制数据被传送到非易失性存储器23以被存储。在该系统的驱动停止之后，从非易失性存储器23读出用于分析异常因子的二进制数据，分析其输出电压为异常的DC / DC转换器的异常的原因。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2007058419A Storage system with logic circuit constructed according to information inside memory on pld 审中-公开
标题翻译：存储系统，根据PLD内存中的信息构建逻辑电路
公开(公告)号：JP2007058419A
公开(公告)日：2007-03-08
申请号：JP2005241198
申请日：2005-08-23
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SASAKURA TAKAHIRO
IPC分类号： G06F3/06 , G11B20/10
CPC分类号： G11C29/52 , G01R31/31816 , G11C2029/0401 , G11C2029/0409
摘要： PROBLEM TO BE SOLVED: To perform control for suppressing deterioration of throughput of a device with a logic circuit constructed according to information inside a memory on a PLD when a soft error occurs in the memory.
SOLUTION: This storage system 100 has: the PLD 217 controlling data transfer between another device 1 and a medium drive 150; and a processor 215. The PLD has: the memory 213 storing information inputted from an information source 15 present outside the PLD; a circuit element group 3 comprising a plurality of circuit elements; and the logic circuit 2 constructed on the circuit element group according to the information inside the memory. The processor detects that the soft error occurs in the memory, detects whether an error occurs in the logic circuit or not, and performs the control according to both results of the detection.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：当在存储器中发生软错误时，执行用于根据PLD上的存储器内的信息构造的逻辑电路来抑制设备的吞吐量恶化的控制。解决方案：该存储系统100具有：控制另一设备1和介质驱动器150之间的数据传输的PLD 217; 和处理器215.PLD具有：存储器213，其存储从存在于PLD外部的信息源15输入的信息; 包括多个电路元件的电路元件组3; 以及根据存储器内的信息在电路元件组上构成的逻辑电路2。处理器检测到存储器中发生软错误，检测逻辑电路中是否发生错误，并根据检测结果进行控制。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2003086754A SEMICONDUCTOR INTEGRATED CIRCUIT MODULE, AND MANUFACTURING METHOD AND USAGE THEREFOR 审中-公开
公开(公告)号：JP2003086754A
公开(公告)日：2003-03-20
申请号：JP2001275887
申请日：2001-09-12
申请人： HITACHI LTD
发明人： SASAKURA TAKAHIRO , ABE SEIICHI
IPC分类号： H01L25/00 , H01L23/24 , H01L23/31 , H01L23/467 , H01L25/10 , H05K1/14 , H05K1/18
摘要： PROBLEM TO BE SOLVED: To solve the problem that the feed distance between a power source and an LSI package cannot be shortened, making it susceptive to power-source fluctuation effects. SOLUTION: A power source module is mounted on the surface of an LSI package. The feed distance between the LSI and the power source module is shortened. As a result, the power source noise is reduced for higher efficiency/ fast response at a power source, resulting in less radiated electromagnetic field. The kinds of power sources (voltages) (w) required for a substrate on which a package is mounted are reduced by allowing each LSI package to contain a required power source module. As a result, mounting efficiency is improved and the substrate is manufactured at a low cost.

4. 发明专利

JPH11250031A PROGRAMMABLE LOGIC AND INFORMATION PROCESSOR 失效
公开(公告)号：JPH11250031A
公开(公告)日：1999-09-17
申请号：JP4580698
申请日：1998-02-26
申请人： HITACHI LTD
发明人： SASAKURA TAKAHIRO , ABE SEIICHI
IPC分类号： G06F7/00 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To realize a diversified and large-scale logic circuit at high speed by a programmable logic comparatively small in configuration scale. SOLUTION: A programmable logic 21 is incorporated in a disk controller 10 and controls data transfer through an HDD(hard disk device) 22 and a disk I/F 23 under control. Two or more memories of a memory A17 and a memory B18 are provided as the memories holding mapping data for realizing desired control logic for an FPGA(field programmable gate array) part 16. A selector 19 which dynamically switches mapping data by selecting data on which memory face is to be used by the FPGA part 16 and a control circuit 15 controlling the operation of the selector 19 and the reading/writing of the contents of the memory A17 and the memory B18 are installed in logic 21. Logic in the EPGA part 16 is switched at high speed by controlling the switch of the memory A17 and the memory B18. Thus, the logic circuit of the diversified/large scale which is above a real logic scale is realized at high speed.

5. 发明专利

JPH09244773A HOT-LINE INSERTION AND EXTRACTION DEVICE 失效
公开(公告)号：JPH09244773A
公开(公告)日：1997-09-19
申请号：JP4743296
申请日：1996-03-05
申请人： HITACHI LTD
发明人： SASAKURA TAKAHIRO , ABE SEIICHI
IPC分类号： G06F1/18 , G06F3/00
摘要： PROBLEM TO BE SOLVED: To provide the hot-line insertion and extraction device which allows nonstop high-line insertion and extraction without using any special interface IC. SOLUTION: Plural packages 1, 2, and 3 are installed by insertion on a back plane board or mother board provided with plural buses 8 and 9 and a power line 10, and when the package 1 is inserted or extracted, the buses and power line are brought into contact with the said package in different timing; and the timing points of contact with the buses and power line are detected, and transfer of one corresponding bus is stopped and reception is made ineffective according to the detection result. At this time, one of the buses 8 and 9 continues to send and receive signals, and consequently hot-line insertion and extraction can be performed without stopping the system on the whole.

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