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1. 发明专利

JPH04205190A IMAGE DATA PROCESSING SYSTEM 失效
公开(公告)号：JPH04205190A
公开(公告)日：1992-07-27
申请号：JP32918790
申请日：1990-11-30
申请人： HITACHI LTD , HITACHI TAGA MOTOR KK
发明人： NAGAOKA MASANOBU , FUJITA KAZUAKI
IPC分类号： G06F17/21 , G06T11/60
摘要： PURPOSE:To eliminate the enlargement and reduction of image data on a document preparing device main body by reading image data from an image input device with the best optional resolution corresponding to the number of display dots of a display device. CONSTITUTION:An operator prepares a target document on the document preparing device over a look at the document on a display device 13. When image input is required according to the contents of the document, an image is inputted from the image input device 3, the display device 13 displays the image, and the operator performs operation for extracting a necessary parts, etc. The main body 11 can detect the maximum number of display dots of the display device 13 in advance. Further, the image input device 3 inputs the image with optional resolution and sets the dot resolution of the read image to an optional value by sending and receiving control commands through an interface cable 15 before the read operation. Consequently, the enlargement and reduction of the image data are eliminated.

2. 发明专利

JPH04152457A IMAGE DATA PROCESSING SYSTEM 失效
公开(公告)号：JPH04152457A
公开(公告)日：1992-05-26
申请号：JP27634290
申请日：1990-10-17
申请人： HITACHI LTD
发明人： NAGAOKA MASANOBU
IPC分类号： G06F17/21 , G06T11/60
摘要： PURPOSE:To change the reading conditions in response to the capacity of a storage by recognizing previously the capacity of the storage and deciding the combination value of the size of a reading area and the image resolution in response to the storage capacity. CONSTITUTION:A main body 11 detects the capacity values of a connected external storage 14 and an internal storage and stores temporarily these capacity values in a main memory. Then, an original image read out of an image input device 3 is shown on a display 15. The combination value of the size of a reading area and the image resolution is decided from the capacities of the storages 14 and 35 which store the detected image data. As a result, the degrees of freedom can be secured for the size of the reading area and the image resolution in response to the capacity of the storage which holds the image data. In addition, the reading conditions are changed in response to the capacity of the storage. Thus, the highly precise image data can be read in a wide area when the storage has a large capacity.

3. 发明专利

JPH0346824B2 失效
公开(公告)号：JPH0346824B2
公开(公告)日：1991-07-17
申请号：JP13628284
申请日：1984-06-29
申请人： HITACHI LTD
发明人： ASAI NOBUTERU , NAGAOKA MASANOBU , MATSUOKA SHIGERU , SATO YUTAKA
IPC分类号： G09G5/24 , G09G1/00 , G09G5/00

4. 发明专利

JPS62203193A IMAGE DISPLAY UNIT 失效
公开(公告)号：JPS62203193A
公开(公告)日：1987-09-07
申请号：JP4416386
申请日：1986-03-03
申请人： HITACHI LTD
发明人： NAGAOKA MASANOBU , ASAI NOBUTERU
IPC分类号： G06F3/153 , G09G1/02 , G09G1/14 , G09G5/00 , G09G5/22 , G09G5/24 , G09G5/36 , G09G5/39 , G09G5/40

5. 发明专利

JPH0327088A DISPLAY CONTROLLER 失效
公开(公告)号：JPH0327088A
公开(公告)日：1991-02-05
申请号：JP16077989
申请日：1989-06-26
申请人： HITACHI LTD
发明人： NAGAOKA MASANOBU
IPC分类号： G09G1/16 , G09G1/00 , G09G5/24
摘要： PURPOSE:To prolong the life of a fluorescent material by displaying all display pattern such as characters in dots when there is an input from an input device within a specific time and ANDing a pattern consisting of alternate dots and its inverted pattern when not. CONSTITUTION:A main body 21 consisting of a CPU 31 composed of a program storage type computer unit, a nonvolatile memory ROM, etc., and includes the main memory 33 consisting of a boot ROM 32 stored with a program to be executed when the power source is turned on and a RAM regarding a document creation device, etc. Then, when there is an input within a preset time interval, the display pattern for a display, etc., are all displayed in dots on a display device 23. When there is no input from the input device 22 within the specific time, on the other hand, a timer 35 operates and an interruption controller 36 can send an interruption signal to the CPU 31.

6. 发明专利

JPH025123A PRINTING SYSTEM 失效
公开(公告)号：JPH025123A
公开(公告)日：1990-01-10
申请号：JP15519988
申请日：1988-06-23
申请人： HITACHI LTD
发明人： NAGAOKA MASANOBU , TAKAGISHI KAZUFUMI
IPC分类号： B41J2/44 , B41J5/30 , G06F3/12 , G06F17/24 , G06K15/00
摘要： PURPOSE:To make it unnecessary to provide each document forming device with a controller by allowing one controller to successively convert document data formed by plural document forming devices into printing dot data in each page to print out them. CONSTITUTION:Only the document forming device 1A, 1B or 1C specified by the controller 21 can transmit/receive information to/from the controller 21. When document data are carried from the device 1A, 1B or 1C selected by the controller 21 through a signal line 3A, 3B or 3C, the document data are converted into printing dot data in each page in accordance with a printing processing program inherent in the device and the dot data are transferred to a printer 22. Thus, the document data formed by respective document forming devices can be successively converted into printing dot data in each page by using one controller 21 for respective document forming device 1A to 1C in common.

7. 发明专利

JPH01140318A SIGNAL TRANSMISSION SYSTEM FOR INPUT DEVICE 失效
公开(公告)号：JPH01140318A
公开(公告)日：1989-06-01
申请号：JP29759987
申请日：1987-11-27
申请人： HITACHI LTD , HITACHI TAGA MOTOR KK
发明人： NAGAOKA MASANOBU , OTSUKI NOBUAKI
IPC分类号： G06F13/00 , G06F3/02
摘要： PURPOSE:To prevent the malfunction of a system from being generated even when an input device receives a disturbance noise by performing data communication by a normal transmission/reception sequence by detecting the abnormal state of the input device immediately even when only one signal line between a processor and the input device is prepared and no reset line is prepared. CONSTITUTION:A monitoring timer 37 is provided at an input device 3 side, and the data transmission output of a microcomputer 33 that is a controller at the input device 3 side is set as a signal from the input device 3 to the processor (main body). And a part of the output is inputted to the clock input of the monitoring timer 37, and the reset output of the monitoring timer 37 is inputted to the reset input of the microcomputer 33. Therefore, it is possible to perform data communication successively without being interrupted by always setting a processor side as a data request side and the input device 3 side as a data delivery side even when only one signal line 32 is prepared and no control line is prepared. In such a way, the malfunction as the system can be prevented from being generated even when abnormality due to the disturbance noise is generated at the input device 3 side.

8. 发明专利

JPS63285626A MEMORY WINDOW SWITCHING DEVICE FOR CPU SYSTEM 失效
公开(公告)号：JPS63285626A
公开(公告)日：1988-11-22
申请号：JP12020287
申请日：1987-05-19
申请人： HITACHI LTD
发明人： NAGAOKA MASANOBU
IPC分类号： G06F12/06 , G06F3/048 , G06F3/14 , G06F13/28
摘要： PURPOSE:To enable each channel of a CPU and a DMA controller to select its own scroll range in case an extended memory space is accessed by a window scroll system, by switching the offset value for each access channel for output of an address signal to an extended memory area. CONSTITUTION:Each channel of a CPU 1 and a DMA controller 2 has its own offset value holding value for window scroll. Then the offset value of said holding means set previously is added with an access address in case he extended memory space 9 is accessed from the CPU 1 or the controller 2. Thus a reading or writing action is possible with a part of the memory 9 through a window space. As a result, each channel of the CPU 1 and the controller 2 can select its own scroll range when the memory 9 is accessed by the window scroll system.

9. 发明专利

JPS61223924A SIGNAL TRANSMITTING SYSTEM 失效
公开(公告)号：JPS61223924A
公开(公告)日：1986-10-04
申请号：JP6390185
申请日：1985-03-29
申请人： HITACHI LTD
发明人： MATSUOKA SHIGERU , NAGAOKA MASANOBU
IPC分类号： G06F3/02 , G06F3/023 , G06F13/42 , G06F17/40 , H03M11/00 , H04L17/00
摘要： PURPOSE:To constitute an input device with a small number of signal lines and to execute efficiently the extracting operation of a key switch by generating a timing based on the extracting operation of the key switch as a reference and synchronizing it when transmitting and receiving a data between a main body and the input device. CONSTITUTION:The RX1 terminal of an operational LSI33 is checked and if it is '0', it is decided to be the head of sending out a scanning start data or sending out a control data and the check of a register A is executed. As a result, in case when it is shown that a reception processing mode or a sending- out data exists, a reception processing or a data sending-out processing and a scanning processing are executed simultaneously and synchronized. I case of transmitting a data, one data length to be sent out is determined based on the number of times of scanning of a key switch as a reference and in case of receiving the data, the timing for inputting one data is determined based on the number of times of scanning of the key switch as a reference.

10. 发明专利

JPS61180354A FAULT DETECTING SYSTEM FOR INPUT DEVICE 失效
公开(公告)号：JPS61180354A
公开(公告)日：1986-08-13
申请号：JP1999185
申请日：1985-02-06
申请人： HITACHI LTD
发明人： NAGAOKA MASANOBU
IPC分类号： G06F3/02 , G06F13/00
摘要： PURPOSE:To detect accurately an abnormal state through a processor by discontinuing the transmission of data for a fixed period of time or longer when an input device has a fault. CONSTITUTION:When an input device 3 has a fault, a reset circuit 60 produces a reset signal 63. a fixed pulse width producing circuit 61 produces a low level pulse signal of a fixed time width, i.e., a data cut-off signal 64 after the signal 63 is supplied. No signal 64 is produced in a normal state and the transmission/ reception of data are carried out normally via a signal line 32. When the signal 63 is produced in an abnormal state, the data sent from a terminal TX1 of an LSI 33 does not emerge on the line 32 owing to an NAND element 62 and are therefore not transmitted to the side of a keyboard 16. While the signal 64 of a fixed time width is produced and therefore the data on the line 32 is kept at a high level while the signal 64 is kept at a low level and as long as no data is sent from a processing IC 30. Then no data is transmitted from the device 3.

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