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1. 发明专利

JP2001085469A ELECTRONIC CIRCUIT DEVICE AND CONTROL METHOD THEREFOR AND CALCULATOR DEVICE USING THE SAME 失效
公开(公告)号：JP2001085469A
公开(公告)日：2001-03-30
申请号：JP25835699
申请日：1999-09-13
申请人： HITACHI LTD
发明人： SAWADA YUMIKO , YAMADA OSAMU , KASAI KENICHI , NEZU TOSHITADA , YAMAMURA HIDEO , KOYANO KOICHI , MARU NAOKI
IPC分类号： H01L21/60
摘要： PROBLEM TO BE SOLVED: To reduce deformation stresses which act between an electronic circuit component and a wiring substrate by providing an electronic circuit device with an electronic circuit part and a plurality of power supplies, and indicating to output a drive signal for driving an electronic circuit component from the power supplies. SOLUTION: An electronic circuit device has an electronic circuit component 1 and a plurality of power supplies 2 and indicates to output a drive signal for driving the electronic circuit component 1 from the power supplies 2 by an indicator 3. A control means 4 controls the indicator 3 to output a drive signal for driving the electronic circuit part 1 at different times each. Therefore, it is possible to reduce generation of vertical stresses in an inside of the electronic circuit 1 by controlling the output of a drive signal from either a power supply 2a or a power supply 2b to stop and to reduce deformation stress, which acts between the electronic circuit 1 and a wiring substrate.

2. 发明专利

JP2001053205A SEALING AND COOLING DEVICE FOR MULTICHIP MODULE 失效
公开(公告)号：JP2001053205A
公开(公告)日：2001-02-23
申请号：JP22205899
申请日：1999-08-05
申请人： HITACHI LTD
发明人： OGURO TAKAHIRO , KASAI KENICHI , NEZU TOSHITADA , KOYANO KOICHI , UDA TAKAYUKI
IPC分类号： H01L23/10 , H01L23/473
摘要： PROBLEM TO BE SOLVED: To uniformly lower the temperature of an LSI efficiently by directly soldering and fixing the sealing top plate of a multichip module, in which a cooling flow-path channel is formed, to the rear of a semiconductor device. SOLUTION: Metalized layers 6 are formed at a position where the rear 24 of a sealing top plate 20, in which a cooling flow-path channel 21 is formed, and the rear 5 of the semiconductor device 10 are faced mutually. Sections among each metalized layer 6 are fixed by soldered joints 26 in the sealing top plate 20 and the semiconductor device 10. Accordingly, the generated heat of LSI chips 1 is passed in microchips, the soldered joints 26 and the sealing top plate 20, and discharged efficiently to a cooling fluid in the cooling flow-path channel 21. Thus, the heat capacity of the sealing top plate 20 can be limited to a small value, thermal strain generated in the case of a temperature rise by heating and in the case of a temperature drop by cooling can be reduced, and productivity such as the assembling properties, disassembling properties or the like of the multichip module can be improved.

3. 发明专利

JPH1166131A CAD AND CAE DEVICE AND ITS ANALYTIC RESULT DISPLAY METHOD 失效
公开(公告)号：JPH1166131A
公开(公告)日：1999-03-09
申请号：JP22618997
申请日：1997-08-22
申请人： HITACHI LTD
发明人： HATA NAOKO , SAITO NAOTO , NEZU TOSHITADA , SAKAMOTO TATSUJI , TAKAHASHI KOICHI
IPC分类号： G06F17/50
摘要： PROBLEM TO BE SOLVED: To efficiently display the analytic result of a large-scale object of analysis having a repetitive structure. SOLUTION: An equivalent model adaptation part 1007 generates an equivalent model for a simple structure by paying attention to the repetitive structure, and calculates physical quantities at its nodes by interpolating the physical quantity of the analytic result obtained by an analysis part 1006 and displays them together with the equivalent model. Further, the part where the maximum physical quantity variation is generated is specified in the display, and the corresponding part of a finite element model and the analytic result of the part are extracated by an analytic result extraction part 1008 and displayed to make the details of the part easy to see.

4. 发明专利

JPH10229262A SURFACE-MOUNT STRUCTURE OF ELECTRONIC PART 失效
公开(公告)号：JPH10229262A
公开(公告)日：1998-08-25
申请号：JP3167397
申请日：1997-02-17
申请人： HITACHI LTD
发明人： WATANABE HIDEKI , IMAI TSUTOMU , NEZU TOSHITADA , KASAI KENICHI , KIZAKI KUNIHIKO
IPC分类号： H05K1/18 , H01H1/00 , H05K3/34 , H05K3/40
摘要： PROBLEM TO BE SOLVED: To enable parts of low cost to be mounted on a wiring board high in mounting density and improved in connection reliability, by a method wherein blind connection holes are provided to the wiring board at positions confronting lead terminals provided to the upside of a package, and only the tips of the lead terminals are fitted in and connected with the connection holes with connecting material. SOLUTION: Blind connection holes 14 are provided to a printed wiring board 15 at positions confronting nail head pins 12 of a PGA(pin grid array) package 11 located over the printed wiring board 15. The inner surface of the connection hole 14 is plated with Cu so as to be improved in solderability. The base of the connection hole 14 is formed like an inverted cone so as to guide the tip of the pin 12 to its center. The tips of the nail head pins 12 are fitted in the connection holes 14. A gap between the tip of the pin 12 and the connection hole 14 is filled up with solder 13 to connect them together.

5. 发明专利

JPH04212439A ELECTRONIC CIRCUIT DEVICE 失效
公开(公告)号：JPH04212439A
公开(公告)日：1992-08-04
申请号：JP6286991
申请日：1991-03-27
申请人： HITACHI LTD
发明人： MATSUI KIYOSHI , SATO RYOHEI , NEZU TOSHITADA , SASAKI HIDEAKI , SHIRAI MITSUGI , HAMAMURA KENICHI
IPC分类号： H01L23/02
摘要： PURPOSE:To disperse the concentration of stress and strain caused by thermal expansion of a ceramic substrate into each of the solder connection parts, by dividing a sealing body into the ceiling panel side and the side panel side. CONSTITUTION:A sealing body is divided into a ceiling panel 9 and side panels 10. When an LSI 4 is operated, the generated heat is conducted to a ceramic substrate 1, in which thermal expansion is generated. The stress and strain generated in this case are applied to solder 6, the side panels 10, and the ceiling panel 9. Since a solder connection part is divided into two parts, i.e., substrate 1-side panel 10 and side panel 10-ceiling panel 9, the strain and stress generated in each solder connection part can be dispersed into each solder connection part. By using the solder 6 connecting substrate 1-side panel 10 and side panel 10-ceiling panel 9, a constant connection height is formed, so that the internal stress and strain in each solder 6 can be reduced.

6. 发明专利

JPH01248596A WIRING BOARD 失效
公开(公告)号：JPH01248596A
公开(公告)日：1989-10-04
申请号：JP7430188
申请日：1988-03-30
申请人： HITACHI LTD
发明人： HIROTA KAZUO , SATO RYOHEI , TAKENAKA TAKATSUGU , NEZU TOSHITADA
IPC分类号： H05K3/46 , H05K7/06
摘要： PURPOSE:To maintain an approximately constant characteristic impedance in wirings employing discrete wires and facilitate suppression of a crosstalk between the wirings by providing grounding wires whose number has a certain ratio to the number of signal wires. CONSTITUTION:LSI's 2 are mounted on a module board 1 and connected to the electrodes on the module board 1 with solder 6 or the like. Wirings 3 are generally composed of covered conductors and the portions of the conductors from which the coverings are removed are connected to the electrodes by wire bonding. A plurality of signal wires are arranged in parallel with each other in a plurality of stages and have a grounding pattern 5 in common. Grounding wires 32 whose number has a certain ratio to the number of the signal wires 31 (one grounding wires to two signal wires) are also provided. Therefore, as the signal wires 31 from the ground pattern 5 do not have the same grounding wire 32 in common, the characteristic impedance of the signal wiring 31 can be approximately constant and a crosstalk can be suppressed.

7. 发明专利

JPS6410634A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6410634A
公开(公告)日：1989-01-13
申请号：JP16536687
申请日：1987-07-03
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： NEZU TOSHITADA , TAKENAKA RYUJI , IMADA HARUHIKO
IPC分类号： H01L21/60 , H05K1/11 , H05K3/34
摘要： PURPOSE:To remove a semiconductor integrated circuit from a wiring board without causing a thermal influence due to mechanical traction or shear by a method wherein a diameter of an electrode on the side of the wiring board is made larger than that of an electrode on the side of the semiconductor integrated circuit. CONSTITUTION:In a semiconductor integrated circuit device where a connection part between a semiconductor integrated circuit 1 and a wiring board 3 is brazed by a phase-down bonding method, a diameter of an electrode 4 on the side of the wiring board 3 is made larger than that of an electrode 2 of the semicondcutor integrated circuit 1 while a tolerance value due to a production process of the wiring board 3 and another tolerance value due to the production process of the diameter 2 on the side of the semiconductor integrated circuit 1 are included. By this setup, when the semiconductor integrated circuit 1 is removed from the wiring board 3, a stress due to mechanical traction or shear is concentrated on the electrode on the side of the semiconductor integrated circuit; the electrode of the semiconductor integrated circuit is cut; accordingly, the semiconductor integrated circuit can be removed without damaging the electrode on the side of the wiring board.

8. 发明专利

JPS63245952A MULTICHIP MODULE STRUCTURE 失效
公开(公告)号：JPS63245952A
公开(公告)日：1988-10-13
申请号：JP7751887
申请日：1987-04-01
申请人： HITACHI LTD
发明人： TAKENAKA TAKATSUGU , NEZU TOSHITADA , SHIGI HIDETAKA , YAMAMOTO MASAKAZU
IPC分类号： H01L23/498 , H01L23/538
摘要： PURPOSE:To obtain the repetitivity of a pattern, and to reduce the numbers of the steps of designing, manufacturing ceramic multilayer substrate, inspecting and repairing by securing a common metallized pattern at each semiconductor mounting site. CONSTITUTION:The wiring patterns of enlarged layer 4, conversion layer 7, power source layer 5 of a ceramic multilayer interconnection substrate 2 are so determined that the lattice point specification on signal wiring layers 6 be come the same in the types of semiconductor elements 1. Thus, the specifications of the connecting pads of the elements 1 and I/O pins 3 can be formed to be the same in the types of the elements 1. Accordingly, the metallized patterns of the layers except the signal line pattern in the substrate 2 are formed to be the same in the types of the elements 1, thereby reducing the number of the steps of designing, manufacturing, inspecting and repairing the substrates.

9. 发明专利

JPS5950598A Method of forming common electrode for electric plating of multialyer circuit board 失效
标题翻译：形成用于多层电路板电镀的共同电极的方法
公开(公告)号：JPS5950598A
公开(公告)日：1984-03-23
申请号：JP15960982
申请日：1982-09-16
申请人： Hitachi Ltd
发明人： TAKENAKA TAKATSUGU , NEZU TOSHITADA , KOBAYASHI FUMIYUKI
IPC分类号： H05K3/46 , H05K3/22 , H05K3/24

10. 发明专利

JP2000349211A SEALING STRUCTURE FOR MULTI-CHIP MODULE 失效
公开(公告)号：JP2000349211A
公开(公告)日：2000-12-15
申请号：JP16204699
申请日：1999-06-09
申请人： HITACHI LTD , HITACHI INFORMATION TECHNOLOGY
发明人： TAKAHASHI KOICHI , KASAI KENICHI , OGURO TAKAHIRO , UDA TAKAYUKI , NEZU TOSHITADA , YAMAGUCHI TAKESHI , MATSUSHITA TAKAHIKO , MARUYAMA OSAMU
IPC分类号： H01L23/36 , H01L23/02 , H01L23/04 , H01L23/40
摘要： PROBLEM TO BE SOLVED: To provide a sealing part structure for a multi-chip module in which cooling performance is stable and sealing-part is reliable. SOLUTION: The lower surface of a frame body 5, whose thermal expansion ratio matches with that of a wiring substrate 1 is bonded to the mounting surface of a semiconductor device 2 of the wiring substrate 1 with a solder 8. A rubber O-ring 15 is inserted between the upper surface of the frame body 5 and the peripheral lower surface of an air-cooling heat sink 7, while a plastic 6 for relative slippage is inserted between the peripheral upper surface of the heat sink 7 and an upper-part frame body 10, to press the upper surface of the plastic 6 at the internal intermediate stage of the upper-part frame body 10, while the lower part of the upper-part frame body 10 and the frame body 5 are clamped with a bolt 9.

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