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1. 发明专利

JP2013073271A Address converter, control method of address converter and arithmetic processing unit 审中-公开
标题翻译：地址转换器，地址转换器和算术处理单元的控制方法
公开(公告)号：JP2013073271A
公开(公告)日：2013-04-22
申请号：JP2011209756
申请日：2011-09-26
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SATO YASUHARU , YAMAZAKI IWAO
IPC分类号： G06F12/12 , G06F12/10
CPC分类号： G06F12/1009 , G06F12/1027
摘要： PROBLEM TO BE SOLVED: To suppress decline of a hit rate of an entry.SOLUTION: In a micro TLB including a CAM part having a plurality of CAM circuits storing address information indicating correspondence of a virtual address and a physical address respectively and a write control part for instructing write of the address information to the CAM circuit indicated by a write pointer when storing new address information, the write pointer is increased when it is indicated that the address information stored in the CAM circuit indicated by the write pointer is used in address conversion, the write of the new address information in the CAM circuit for which use of the address information is indicated is avoided, the lately used address information is held, and the decline of the hit rate is suppressed.
摘要翻译：要解决的问题：抑制条目命中率的下降。解决方案：在包括具有多个CAM电路的CAM部分的微型TLB中，分别存储指示虚拟地址和物理地址的对应关系的地址信息，以及用于指示将地址信息写入指示的CAM电路的写入控制部分当存储新地址信息时，通过写指针，当指示存储在由写指针指示的CAM电路中的地址信息用于地址转换时，写指针增加，在CAM电路中写新地址信息为了避免使用地址信息，保持最近使用的地址信息，并且抑制命中率的下降。版权所有（C）2013，JPO＆INPIT

2. 发明专利

JP2011086820A Multi-chip module 有权
标题翻译：多芯片模块
公开(公告)号：JP2011086820A
公开(公告)日：2011-04-28
申请号：JP2009239489
申请日：2009-10-16
申请人： Fujitsu Ltd , Fujitsu Semiconductor Ltd , 富士通セミコンダクター株式会社 , 富士通株式会社
发明人： KOIDE MASATERU , MIZUTANI DAISUKE , INOUE AIICHIRO , YAMASHITA HIDEO , YAMAZAKI IWAO , KATO MASAYUKI , UENO SEIJI , IMAMURA KAZUYUKI
IPC分类号： H01L25/04 , H01L23/52 , H01L25/18
CPC分类号： H01L23/49827 , H01L23/49822 , H01L23/66 , H01L24/16 , H01L25/0655 , H01L2224/131 , H01L2224/16235 , H01L2224/73253 , H01L2924/0001 , H01L2924/01078 , H01L2924/10253 , H01L2924/014 , H01L2224/13099 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To shorten the wiring lengths among LSI chips in a multi-chip module. SOLUTION: A plurality of LSI chips 30A-30D are arranged on a silicon interposer 20 with a wiring pattern 26a and each of the LSI chips is connected to the other LSI chips via the wiring pattern 26a, and the plurality of LSI chips and a base substrate 10 are electrically connected to each other via a portion excluding the wiring pattern 26a. In this case, the silicon interposer 20 can be manufactured separately from the base substrate, thereby making a wiring pattern into a micropattern. As a result, the wiring pattern can be made short, and wiring lengths among LSI chips can be shortened also. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：缩短多芯片模块中的LSI芯片之间的布线长度。解决方案：多个LSI芯片30A-30D布置在具有布线图案26a的硅插入件20上，并且每个LSI芯片经由布线图案26a连接到其它LSI芯片，并且多个LSI芯片并且基底基板10经由除布线图案26a之外的部分彼此电连接。在这种情况下，可以与基底基板分开制造硅插入件20，从而将布线图案形成为微图案。结果，可以缩短布线图案，并且也可以缩短LSI芯片之间的布线长度。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2010218367A Processing apparatus and method for acquiring log information 有权
标题翻译：处理装置和采集日志信息的方法
公开(公告)号：JP2010218367A
公开(公告)日：2010-09-30
申请号：JP2009065959
申请日：2009-03-18
申请人： Fujitsu Ltd , 富士通株式会社
发明人： YAMAZAKI IWAO , HARA MITSUHARU , YAMANAKA EIJI
IPC分类号： G06F11/34 , G06F11/28
CPC分类号： G05B19/042 , G06F11/3466 , G06F11/3476 , G06F2201/88 , G06F2201/885
摘要： PROBLEM TO BE SOLVED: To provide a technique for examining an operation state inside a processing apparatus when a user program is executed. SOLUTION: A processing apparatus includes a processor that executes an execution object program including a series of instructions. The processing apparatus is provided with: a log recording unit configured to record an operation log of the processing apparatus; a managing unit configured to control a recording operation performed by the log recording unit and to read the operation log recorded in the log recording unit; an input unit configured to detect, from among the series of instructions of the execution object program, a start instruction that starts a process for delivering a control instruction destined for the managing unit to the managing unit, and to deliver the control instruction to the managing unit in response to the start instruction; and an output unit configured to receive the operation log read by the managing unit from the managing unit. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于在执行用户程序时检查处理装置内的操作状态的技术。解决方案：处理装置包括执行包括一系列指令的执行对象程序的处理器。该处理装置设置有：记录处理装置的操作日志的日志记录单元; 管理单元，被配置为控制由所述日志记录单元执行的记录操作并且读取记录在所述日志记录单元中的操作日志; 输入单元，被配置为从所述执行对象程序的一系列指令中检测开始指令，所述开始指令开始用于将用于所述管理单元的控制指令发送到所述管理单元的处理，并且将所述控制指令传递到所述管理响应于开始指令的单位; 以及输出单元，被配置为从管理单元接收由管理单元读取的操作日志。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2008165449A Error correction code generation method and memory control device 有权
标题翻译：错误校正代码生成方法和存储器控制器件
公开(公告)号：JP2008165449A
公开(公告)日：2008-07-17
申请号：JP2006353505
申请日：2006-12-27
申请人： Fujitsu Ltd , 富士通株式会社
发明人： HIRANO TAKAHITO , MIURA TAKASHI , YAMAZAKI IWAO
IPC分类号： G06F12/08 , G06F12/16
CPC分类号： G06F11/1064 , G11C2029/0411
摘要： PROBLEM TO BE SOLVED: To generate a correct error correction code even when any RAM error occurs before storage data are actually written in a cache memory(RAM) after confirming that there is no error in cache line data to be stored. SOLUTION: The cache line data to be stored are stored in a register before writing the storage data, and the storage data are written in a cache memory, and the register storage content and the store data are merged, and an error correction code is generated with respect to the merge result. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：即使在存储数据被实际写入高速缓存存储器（RAM）中之后，即使在存储数据没有错误的高速缓存行数据中没有发生任何RAM错误发生时，也可以生成正确的纠错码。解决方案：在写入存储数据之前，要存储的高速缓存行数据被存储在寄存器中，并且将存储数据写入高速缓存存储器中，并且将存储器存储内容和存储数据合并，并进行纠错相对于合并结果生成代码。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2006040091A Address conversion information storage device and address conversion information storage method 有权
标题翻译：地址转换信息存储设备和地址转换信息存储方法
公开(公告)号：JP2006040091A
公开(公告)日：2006-02-09
申请号：JP2004221216
申请日：2004-07-29
申请人： Fujitsu Ltd , 富士通株式会社
发明人： DOI MASANORI , YAMAZAKI IWAO , HONKURUMADA TSUTOMU , DOTEGUCHI MASAHIRO
IPC分类号： G06F12/10 , G06F12/08
CPC分类号： G06F12/1018 , G06F12/1027 , G06F12/1036
摘要： PROBLEM TO BE SOLVED: To provide an address conversion information storage device and an address conversion information storage method capable of efficiently preventing a slashing phenomenon.
SOLUTION: Information of a context related to a virtual address 10 is acquired from a bit string of 0 bit to 8 bit of a context register 11. Based on the acquired information of the context and information of a bit string of 22 bit to 30 bit of the virtual address 10, the value of a TLB (translation lookaside buffer) index address showing a storage position for storing information related to address conversion between the virtual address 10 and an actual address is determined by use of a hash circuit 13.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供能够有效地防止削减现象的地址转换信息存储装置和地址转换信息存储方法。解决方案：从上下文寄存器11的0位到8位的比特串中获取与虚拟地址10相关的上下文的信息。根据获取的上下文的信息和22位的比特串的信息到虚拟地址10的30比特，通过使用散列电路13来确定示出用于存储与虚拟地址10和实际地址之间的地址转换相关的信息的存储位置的TLB（转换后备缓冲器）索引地址的值（C）2006年，JPO＆NCIPI

6. 发明专利

JP2006039968A Address conversion buffer control device and address conversion buffer control method 有权
标题翻译：地址转换缓冲器控制设备和地址转换缓冲器控制方法
公开(公告)号：JP2006039968A
公开(公告)日：2006-02-09
申请号：JP2004219234
申请日：2004-07-27
申请人： Fujitsu Ltd , 富士通株式会社
发明人： DOI MASANORI , YAMAZAKI IWAO
IPC分类号： G06F12/10 , G06F9/46 , G06F12/08
CPC分类号： G06F12/1027
摘要： PROBLEM TO BE SOLVED: To realize a processor capable of simultaneously executing a plurality of threads on one core without increasing the capacity of an address conversion buffer.
SOLUTION: A retreat area control part 210 ensures an area for retreating information of CAM 110 which cannot be shared by a plurality of threads in a RAM 120. When a tread to be executed on the processor is switched, a retreat data transcribing part 220 acquires information corresponding to a newly executed tread from the RAM 120 and transcribes it to the CAM 110. ECC data are added to information to be retreated to the RAM 120 to ensure the reliability of data.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：实现能够在不增加地址转换缓冲器的容量的情况下在一个核上同时执行多个线程的处理器。解决方案：撤退区域控制部分210确保用于撤回CAM 110的信息的区域，其不能由RAM 120中的多个线程共享。当切换要在处理器上执行的踏板时，撤回数据转录部分220从RAM 120获取与新执行的胎面相对应的信息，并将其转录到CAM 110.将ECC数据添加到要退回到RAM 120的信息，以确保数据的可靠性。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2011150691A Arithmetic processing unit, information processing device, and control method 有权
标题翻译：算术处理单元，信息处理设备和控制方法
公开(公告)号：JP2011150691A
公开(公告)日：2011-08-04
申请号：JP2010264381
申请日：2010-11-26
申请人： Fujitsu Ltd , 富士通株式会社
发明人： YAMAZAKI IWAO , IMAI HIROYUKI
IPC分类号： G06F9/318 , G06F9/30 , G06F12/08
CPC分类号： G06F9/30047 , G06F9/3017 , G06F9/30189
摘要： PROBLEM TO BE SOLVED: To easily read a result of a cache hit check without a dedicated transfer bus.
SOLUTION: An arithmetic processing unit 10 has a debug flag bit 31a that indicates whether to perform the cache hit check to check a cache state. When the flag bit indicates to perform the cache hit check and a prefetch instruction is received, the prefetch instruction is extended to perform the cache hit check. When the cache hit check is performed, the arithmetic processing unit 10 stores a result of the cache hit check in an L1 hit information register 32 to read the cache hit check result stored in hit information registers 23 and 32.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了容易地读取没有专用传输总线的高速缓存命中检查的结果。解决方案：算术处理单元10具有调试标志位31a，其指示是否执行高速缓存命中检查以检查高速缓存状态。当标志位指示执行高速缓存命中检查并且接收到预取指令时，预取指令被扩展以执行高速缓存命中检查。当执行高速缓存命中检查时，算术处理单元10将高速缓存命中检查的结果存储在L1命中信息寄存器32中，以读取存储在命中信息寄存器23和32中的高速缓存命中检查结果。 C）2011，JPO＆INPIT

8. 发明专利

JP2011138211A Error controller, processor core, arithmetic processor, information processor, and pseudo error control method 有权
标题翻译：错误控制器，处理器核，算术处理器，信息处理器和PSEUDO错误控制方法
公开(公告)号：JP2011138211A
公开(公告)日：2011-07-14
申请号：JP2009296260
申请日：2009-12-25
申请人： Fujitsu Ltd , 富士通株式会社
发明人： YAMAZAKI IWAO
IPC分类号： G06F11/22
CPC分类号： H04L1/241 , G06F11/2215 , G06F11/267
摘要： PROBLEM TO BE SOLVED: To obtain an error controller in consideration of the propagation delay of a signal on the generation of a pseudo error, and also to provide a processor core, and a pseudo error control method. SOLUTION: Pseudo error generating devices 30_1 to 30_n for generating the pseudo error are arranged in the neighborhood of error generation target circuits 40_1 to 40_n. A pseudo error controller 20 selects one of the pseudo error generating devices 30_1 to 30_n and sets an error content in a local error mode register 31. The pseudo error generating devices 30_1 to 30_n monitor the generation of an event corresponding to the error content so as to notify the pseudo error controller 20 of the generation. The pseudo error controller 20 instructs the generation of the error to the pseudo error generating devices 30_1 to 30_n, based on the times of generation of the event. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：考虑到信号在产生伪误差时的传播延迟，以及提供处理器核心和伪误差控制方法，以获得误差控制器。解决方案：用于产生伪误差的伪错误产生装置30_1至30_n被布置在错误产生目标电路40_1至40_n附近。伪错误控制器20选择伪错误产生装置30_1至30_n中的一个，并在本地错误模式寄存器31中设置错误内容。伪错误产生装置30_1至30_n监视与错误内容相对应的事件的生成，以便以通知伪错误控制器20的生成。伪错误控制器20基于事件的生成次数，向伪错误生成装置30_1〜30_n指示生成错误。版权所有（C）2011，JPO＆INPIT

9. 发明专利

JP2006040143A Information processor and store instruction control method 有权
标题翻译：信息处理器和存储指令控制方法
公开(公告)号：JP2006040143A
公开(公告)日：2006-02-09
申请号：JP2004222044
申请日：2004-07-29
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MIURA TAKASHI , YAMAZAKI IWAO
IPC分类号： G06F9/38 , G06F12/00 , G06F12/08
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3826 , G06F9/3834 , G06F9/3842 , G06F9/3861
摘要： PROBLEM TO BE SOLVED: To enhance use efficiency of an arithmetic register which holds store data when a store instruction to store data in a predetermined storage area on a main memory or on a cache memory is executed. SOLUTION: This information processor is constituted so that an instruction processing part 10 issues, when the arithmetic register 22 in which an arithmetic result is held is established, an arithmetic result from the arithmetic register 22 to store data buffers 50-0 to 50-n as store data and is provided with a suppressing part 82 which suppresses setting of a store data holding flag 30d to an off state by a reset part 81 at the point of time when the store instruction is held in store ports 30-0 to 30-n and maintains an on state of the store data holding flag 30d when the store data are held in the store data buffers 50-0 to 50-n before the store instruction is held in the store ports 30-0 to 30-n. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：当执行在主存储器或高速缓冲存储器上的预定存储区域中存储数据的存储指令时，提高保存存储数据的算术寄存器的使用效率。解决方案：该信息处理器被构造成使得指令处理部分10在其中保存算术结果的算术寄存器22被建立时发出来自算术寄存器22的算术结果，以将数据缓冲器50-0存储到 50-n作为存储数据，并且设置有抑制部分82，其抑制在存储指令被保存在存储端口30-0中的时间点处由复位部分81将存储数据保持标志30d设置为关闭状态当将存储数据保存在存储数据缓冲器50-0至50-n中之前，存储数据保持标志30d保持在存储指令30-0至30- ñ。版权所有（C）2006，JPO＆NCIPI

10. 发明专利

JP2006040140A Information processor and multi-hit control method 有权
标题翻译：信息处理器和多重控制方法
公开(公告)号：JP2006040140A
公开(公告)日：2006-02-09
申请号：JP2004222041
申请日：2004-07-29
申请人： Fujitsu Ltd , 富士通株式会社
发明人： HIRANO TAKAHITO , YAMAZAKI IWAO , HONKURUMADA TSUTOMU
IPC分类号： G06F12/10 , G06F9/46
CPC分类号： G06F12/1036 , G06F12/1045
摘要： PROBLEM TO BE SOLVED: To share a buffer for address conversion (TLB: Translation Lookaside Buffer) among a plurality of threads without generating unnecessary multi-hit in an information processor which operates by a multithread system. SOLUTION: The information processor is provided with the TLB 31 which holds address conversion pairs and thread information, a retrieval part 32 which retrieves an address conversion pair of the same virtual address as a virtual address to be converted into a physical address so as to convert the virtual address into the physical address from the TLB 31, a judgment part 34 which judges, when a plurality of address conversion pairs are retrieved by the retrieval part 32, whether or not two or more pieces of thread information among a plurality of pieces of thread information corresponding to the plurality of address conversion pairs are the same and a multi-hit control part 35 which suppresses output of the multi-hit and executes address conversion when it is judged that the pieces of thread information are different by the judgment part 34. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：在多个线程之间共享用于地址转换的缓冲器（TLB：Translation Lookaside Buffer），而不会在由多线程系统操作的信息处理器中产生不必要的多次命中。解决方案：信息处理器设置有保存地址转换对和线程信息的TLB 31，检索部分32，其检索与要转换为物理地址的虚拟地址相同的虚拟地址的地址转换对，从而为了从TLB 31将虚拟地址转换成物理地址，判断部分34当多个地址转换对被检索部分32检索时判断多个线程信息是否为多个与多个地址转换对相对应的线程信息相同;多命中控制部分35，当判断出线程信息不同时，抑制多次命中的输出并执行地址转换判决第34条。版权所有（C）2006年，JPO＆NCIPI

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