专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2013146007A Transmitting circuit, receiving circuit, transmitting method and receiving method 有权
标题翻译：发送电路，接收电路，发送方法和接收方法
公开(公告)号：JP2013146007A
公开(公告)日：2013-07-25
申请号：JP2012006055
申请日：2012-01-16
申请人： Fujitsu Ltd , 富士通株式会社 , Fujitsu Telecom Networks Ltd , 富士通テレコムネットワークス株式会社
发明人： KANEMORI WATARU , RYU MASAMICHI , FUKUDA NAOKI , MAJIMA SATORU , HISAMA KAZUNORI , TAKESHITA NAOYUKI , WATANABE JUNJI
IPC分类号： H04L29/06
摘要： PROBLEM TO BE SOLVED: To improve the certainty of reducing the number of appearance of specific data, through scrambling.SOLUTION: A transmitting circuit 24 comprises scramble circuits (34, 37) for scrambling a payload, a determination circuit 35 for determining whether at least one of a generation polynomial and an initial value to be used by the scramble circuits (34, 37) is appropriate, a control circuit 36 for changing at least one of the generation polynomial and the initial value that the scramble circuits (34, 37) use when at least one of the generation polynomial and the initial value is not appropriate, and a multiplexing circuit 38 which multiplexes information for identifying at least one of the generation polynomial and the initial value used for scrambling the payload stored in a packet, to the packet.
摘要翻译：要解决的问题：通过加扰来提高减少特定数据出现次数的确定性。解决方案：发送电路24包括用于加扰有效载荷的扰频电路（34,37），确定电路35，用于确定是否至少用于加扰电路（34,37）使用的生成多项式和初始值之一是适用的，用于改变加扰电路（34,37）的生成多项式和初始值中的至少一个的控制电路36，在生成多项式和初始值中的至少一个不适用的情况下使用多路复用电路38，其将用于识别用于将存储在分组中的有效载荷进行加扰的生成多项式和初始值中的至少一个的信息复用到包。

2. 发明专利

JP2010233105A Error correction control apparatus, error correction control method, and media data distribution system 有权
标题翻译：错误校正控制装置，错误校正控制方法和媒体数据分发系统
公开(公告)号：JP2010233105A
公开(公告)日：2010-10-14
申请号：JP2009080358
申请日：2009-03-27
申请人： Fujitsu Ltd , 富士通株式会社
发明人： DOI KAZUMI , ENDO ATSUSHI , ABE MASAHIRO , TAKESHITA NAOYUKI , KAMITO TAKAFUMI , ONIMARU KOICHI , UMEMOTO YASUTAKA , IHARA NORIYUKI
IPC分类号： H04L1/00 , H04N7/173 , H04N21/438
CPC分类号： H03M13/373 , H03M13/2906 , H03M13/6547 , H04L1/0052
摘要： PROBLEM TO BE SOLVED: To reduce the delay time until the start of decoding processing, thereby suppressing the burst amount. SOLUTION: A decoding device 1 includes a media packet receiving section 11 for receiving a plurality of packets configured in plural rows and columns; an FEC-packet receiving section 12 for receiving plural error correction packets which are generated for each row and each column of the packets and which include matrix configuration information of the plural packets; an accumulated packet number determining section 22 for determining the minimum number of accumulated packets for restoring a lost packet, based on the matrix configuration information of the packets included in the received error correction packets; a buffer control section 24 for accumulating packets received for the determined number of accumulated packets and the error correction packets received at the same timing as for those packets; and a restoration processing section 23 for restoring the packet concerned, by using the accumulated packets and the error correction packets, when a packet loss is detected. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了减少直到解码处理开始的延迟时间，从而抑制突发量。解决方案：解码装置1包括用于接收多个行和列配置的多个分组的媒体分组接收部分11; FEC分组接收部分12，用于接收针对每个分组的每一行和每一列生成并包括多个分组的矩阵配置信息的多个纠错分组; 累积分组数确定部分22，用于根据接收到的纠错分组中包括的分组的矩阵配置信息确定用于恢复丢失分组的累积分组的最小数目; 缓冲器控制部分24，用于累积针对所确定数量的累积分组接收到的分组和在与这些分组相同的定时接收的纠错分组; 以及恢复处理部23，用于当检测到分组丢失时，通过使用累积的分组和纠错分组来恢复相关的分组。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2010279082A Image processing system 有权
标题翻译：图像处理系统
公开(公告)号：JP2010279082A
公开(公告)日：2010-12-09
申请号：JP2010204957
申请日：2010-09-13
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KAYASHIMA TADASHI , OHASHI TAKATO , OTSURU HIROSHI , TAKESHITA NAOYUKI , YAMASHITA KAZUHIRO , YAMAGUCHI YOSUKE , ICHIKI ATSUSHI , FUJITA MAKOTO
IPC分类号： H04N19/00 , H04N19/436 , H04N19/70
摘要： PROBLEM TO BE SOLVED: To properly display high-resolution video signals. SOLUTION: Each of a plurality of encoding devices calculates as a first time a value by adding an encoding delay time determined in common among the plurality of encoding devices, to a value of a system time clock (STC) counter. Each encoding device then transfers a system stream created by including the calculated first time to a corresponding decoding device which corresponds one-to-one with the encoding device among a plurality of decoding devices configuring a decoding system. Each of the plurality of decoding devices adds a stream fluctuation value that is a fluctuation generated among the plurality of decoding devices in output time and decoding delay time, and calculates as a second time a value by adding the first time to a maximum value decided in common among the plurality of decoding devices as the probably highest added values. Each decoding device then outputs divided image data decoded from the system stream to a composite section that combines the image data with the calculated second time. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：正确显示高分辨率视频信号。解决方案：多个编码装置中的每一个通过将在多个编码装置中共同确定的编码延迟时间相加到系统时钟（STC）计数器的值而首次计算值。然后，每个编码装置在构成解码系统的多个解码装置之间，将通过将计算出的第一次的计算而生成的系统流传送到与编码装置一对一对应的解码装置。多个解码装置中的每一个在输出时间和解码延迟时间中添加作为在多个解码装置中产生的波动的流波动值，并且通过将第一时间加到由在多个解码装置中共同作为可能最高的附加值。每个解码装置然后将从系统流解码的分割图像数据输出到组合图像数据与计算的第二次的复合部分。版权所有（C）2011，JPO＆INPIT

4. 发明专利

JP2008061151A Motion picture processing apparatus and prefetch control method 有权
标题翻译：运动图像处理装置和预制控制方法
公开(公告)号：JP2008061151A
公开(公告)日：2008-03-13
申请号：JP2006238457
申请日：2006-09-04
申请人： Fujitsu Ltd , 富士通株式会社
发明人： WATABE YASUHIRO , WAKAYOSHI MITSUHARU , TAKESHITA NAOYUKI
IPC分类号： G06T1/60 , G06F12/08 , H04N19/00 , H04N19/423 , H04N19/44
CPC分类号： G06F12/0862 , H04N19/433 , H04N19/61
摘要： PROBLEM TO BE SOLVED: To provide a motion picture processing apparatus which improves a hit rate for a prefetch memory of a request of reading a rectangular region in a decoding screen from a predetermined circuit section. SOLUTION: A hit/mishit determining/counting section 14 determines whether a rectangular reading request issued from a decoding processing section 13 hits the prefetch memory 15. In the case of hit, the section 14 issues the rectangular reading request for the prefetch memory 15. In the case of mishit, the section 14 issues the rectangular reading request for an external memory control section 12 in case of mishit. Further, the section 14 counts the number of hits and the number of mishits for each of mishit types. Every time a decoding processing section 13 completes decoding processing per macroblock line, a prefetch control section 18 adjusts an upadate vertical size of a prefetch region on the basis of the number of hits of a rectangular reading request issued by the decoding processing section 13 in decoding processing of the macroblock line, and of the number of mishits per mishit type. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种运动图像处理装置，其从预定电路部分提高在解码屏幕中读取矩形区域的请求的预取存储器的命中率。点击/确定/计数部分14确定从解码处理部分13发出的矩形读取请求是否触发预取存储器15.在命中的情况下，部分14发出用于预取的矩形读取请求存储器15.在虚构的情况下，在虚构的情况下，部分14发出外部存储器控制部分12的矩形读取请求。此外，第14节计算每个mishit类型的命中数和个数。每次解码处理部分13完成每个宏块行的解码处理时，预取控制部分18根据由解码处理部分13在解码中发出的矩形读取请求的命中次数来调整预取区域的上限垂直大小宏块行的处理，以及每个mishit类型的mishits的数量。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2008059496A Moving image processor 有权
标题翻译：移动图像处理器
公开(公告)号：JP2008059496A
公开(公告)日：2008-03-13
申请号：JP2006238511
申请日：2006-09-04
申请人： Fujitsu Ltd , 富士通株式会社
发明人： WATABE YASUHIRO , WAKAYOSHI MITSUHARU , TAKESHITA NAOYUKI
IPC分类号： G06F12/08 , G06F12/00 , G06F12/02 , G06F12/06 , H04N19/00 , H04N19/423 , H04N19/44 , H04N19/85
摘要： PROBLEM TO BE SOLVED: To provide a moving image processor capable of reducing wait conditions due to accesses from a plurality of memory access sources to a prefetch memory for improving efficiency of moving image processing.
SOLUTION: The prefetch memory 35 is constructed of four memories 38_0 to 38_3 accessible independently. The moving image processor is provided with an address generation circuit 40 for a decode processing part 33, an address generation circuit 41 for a decode processing part 34, an address generation circuit 42 for a prefetch memory update control part 36, and a used/unused flag register 44 showing whether each of the memories 38_0 to 38_3 is accessed or not. By referring to the used/unused flag register 44, an arbitration circuit 43 allows a plurality of parallel memory accesses on condition that no collision occurs between accesses to the same memory in the memory 38_0 to 38_3 by the decode processing part 33, the decode processing part 34, and the prefetch memory update control part 36.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种运动图像处理器，其能够将由于从多个存储器访问源的访问减少到预取存储器的等待条件，以提高运动图像处理的效率。解决方案：预取存储器35由可独立访问的四个存储器38_0至38_3构成。运动图像处理器设置有用于解码处理部分33的地址产生电路40，用于解码处理部分34的地址产生电路41，用于预取存储器更新控制部分36的地址产生电路42，以及使用/未使用的标志寄存器44示出是否访问了存储器38_0至38_3中的每一个。通过参考使用/未使用的标志寄存器44，仲裁电路43允许多个并行存储器访问，条件是在由解码处理部分33访问存储器38_0至38_3中的相同存储器之间不发生冲突，解码处理第34部分和预取存储器更新控制部分36.版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2008166862A Encoding and decoding system, encoding system, and decoding system 有权
标题翻译：编码和解码系统，编码系统和解码系统
公开(公告)号：JP2008166862A
公开(公告)日：2008-07-17
申请号：JP2006350521
申请日：2006-12-26
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KAYASHIMA TADASHI , OHASHI TAKATO , OOTSURU HIROSHI , TAKESHITA NAOYUKI , YAMASHITA KAZUHIRO , YAMAGUCHI YOSUKE , ICHIKI ATSUSHI , FUJITA MAKOTO
IPC分类号： H04N19/436 , H04N19/00 , H04N19/70
CPC分类号： H04N21/4305 , H04N19/436 , H04N21/2365 , H04N21/242 , H04N21/4307 , H04N21/4347
摘要： PROBLEM TO BE SOLVED: To correctly display a motion image signal of high resolution. SOLUTION: A plurality of encoding devices each calculate as first time a value obtained by adding an encoding delay time determined in common among the plurality of encoding devices to a value of an STC counter, and transmit a system stream generated including the calculated first time to a decoding device made to correspond to the encoding device one to one among a plurality of decoding devices constituting a decoding system. The plurality of decoding devices each calculate as second time a value obtained by adding a decoding delay time to a value of stream fluctuation as fluctuation generated among the plurality of encoding devices as to output time and then adding the first time to a maximum value determined in common among the plurality of decoding devices as a value being possible a maximum value of the addition value, and outputs divided image data decoded from the system stream to a composing unit which puts the image data together at the calculated second time. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：正确显示高分辨率的运动图像信号。解决方案：多个编码装置各自计算通过将多个编码装置中共同确定的编码延迟时间与STC计数器的值相加而获得的值，并且发送包括计算出的所述编码装置的系统流首先，在构成解码系统的多个解码装置中，对应于编码装置一个一个地进行解码的装置。多个解码装置各自计算通过将解码延迟时间与流波动的值相加而获得的值，作为在多个编码装置之间产生的关于输出时间的波动，然后将第一时间添加到确定的最大值在多个解码装置中共同的值作为相加值的最大值，并且将从系统流解码的分割图像数据输出到将所述图像数据放在一起计算的第二次的合成单位。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2005039522A Wireless lan data transmission system, method for transmitting wireless lan data and wireless lan data transmission program 有权
标题翻译：无线LAN数据传输系统，无线局域网数据传输方法及无线局域网数据传输方案
公开(公告)号：JP2005039522A
公开(公告)日：2005-02-10
申请号：JP2003274463
申请日：2003-07-15
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MIYAJIMA SHINICHIRO , ICHIYANAGI KAZUHIRO , KUSUMOTO AKIKO , NAGANO YUJI , EGUCHI KATSUHIRO , TAKESHITA NAOYUKI , ISHII YUJI , IMOTO KAZUYUKI
IPC分类号： H04L12/28 , H04W36/06 , H04W36/08 , H04Q7/22 , H04Q7/38
CPC分类号： H04W36/02
摘要： PROBLEM TO BE SOLVED: To improve the transmission efficiency of data and to transmit data of high quality by securing the continuity of data in a wireless communication system.
SOLUTION: If communication between a wireless LAN device 200 and a 1st access point 221 is disabled when the wireless LAN device 200 tries to move from a communication area of the 1st access point 221 to a communication area of a 2nd access point 222, a memory control part 206 stops data transmission to the 1st access point 221. In this case, the data to be transmitted to the 1st access point 221 are still stored in a memory 207. After the wireless LAN device 200 entered the communication area of the 2nd access point 222, the memory control part 206 restarts the transmission of untransmitted data previously stored in the memory 207. Then the transmission of data following the untransmitted data is started.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过确保无线通信系统中的数据的连续性来提高数据的传输效率和传输高质量的数据。解决方案：当无线LAN设备200尝试从第一接入点221的通信区域移动到第二接入点222的通信区域时，如果无线LAN设备200与第一接入点221之间的通信被禁用存储器控制部分206停止向第一接入点221的数据传输。在这种情况下，要发送到第一接入点221的数据仍然存储在存储器207中。在无线LAN设备200进入通信区域第二接入点222，存储器控制部分206重新开始先前存储在存储器207中的未发送数据的传输。然后开始发送未发送数据之后的数据。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JPH1042298A PICTURE CORRELATION UNIT 失效
公开(公告)号：JPH1042298A
公开(公告)日：1998-02-13
申请号：JP19198096
申请日：1996-07-22
申请人： FUJITSU LTD
发明人： YAMORI AKIHIRO , KOBAYAKAWA TAKAHIRO , TAKESHITA NAOYUKI
IPC分类号： H04N19/50 , G06T1/00 , H04N19/423 , H04N19/436 , H04N19/503 , H04N19/51 , H04N7/32
摘要： PROBLEM TO BE SOLVED: To shorten operation necessary time by correlating frames in parallel by means of a pipeline system against the combination of a segment picture element value string and a reference picture element value string on n-pieces of scanning periods divided at every scanning line. SOLUTION: A block storage means 11 outputs the reference picture element value string to an address. A first delay means 12 gives delay (i-1)t to the address in the scanning period T of k-picture element. A plurality of reference picture storage means 13 output the reference picture element corresponding to the first delay address in the reference picture element string of kX picture element from the ((i-1)kX+1)-th picture element at every scanning line. A second delay means 14 individually gives kn-pieces of delays (j-1)t as against an integer (j) to the reference picture element value string for the scanning period (t) of the X picture element. A timing adjusting means 15 outputs kn-pieces of segment picture element value strings constituted of adjacent (2X-1)-pieces of picture element values in parallel on the common scanning line to the picture element value at the head by detaching the picture element value at the head by X-pieces from the reference picture element value string in the order of scanning. A correlation means 16 correlates the reference picture element value string outputted from the second delay means 14 in the ascending order of the integer (j) and the kn-pieces of segment picture element value strings.

9. 发明专利

JP2002027482A PICTURE CODING SYSTEM 失效
公开(公告)号：JP2002027482A
公开(公告)日：2002-01-25
申请号：JP2000208741
申请日：2000-07-10
申请人： FUJITSU LTD
发明人： TAKESHITA NAOYUKI , SAKAI KIYOSHI , HAMANO TAKASHI , KAMITO TAKAFUMI
IPC分类号： H04N5/92 , H03M7/30 , H04N5/956 , H04N19/12 , H04N19/126 , H04N19/134 , H04N19/136 , H04N19/14 , H04N19/152 , H04N19/157 , H04N19/172 , H04N19/176 , H04N19/196 , H04N19/423 , H04N19/426 , H04N19/50 , H04N19/503 , H04N19/577 , H04N19/60 , H04N19/61 , H04N19/625 , H04N19/90 , H04N19/91 , H04N19/93 , H04N7/32 , H04N7/30
摘要： PROBLEM TO BE SOLVED: To realize preprocessing of coding such as reorder processing and absorption processing of asynchronism with minimum memory size in a picture coding system even for a large volume picture data to be coded. SOLUTION: The picture coding system comprises a compression section 2 for compressing input picture data to be coded, a memory section 4 for storing the input picture data compressed in the compression section 2 for given preprocessing of coding, an expanding section 5 for expanding the compressed picture data stored in the memory section 4 into the original input picture data, and a coding section 6 for coding the input picture data expanded in the expanding section 5.

10. 发明专利

JPH08275175A DIGITAL IMAGE DECODER 失效
公开(公告)号：JPH08275175A
公开(公告)日：1996-10-18
申请号：JP7258195
申请日：1995-03-30
申请人： FUJITSU LTD
发明人： WATANABE HIDEAKI , OTA MITSUHIKO , KONO TADAMI , MIYAWAKI KATSUKI , MIYASAKA HIDEKI , TAKESHITA NAOYUKI
IPC分类号： H04N11/04 , H03M7/00 , H04N19/102 , H04N19/134 , H04N19/137 , H04N19/172 , H04N19/189 , H04N19/196 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/50 , H04N19/503 , H04N19/51 , H04N19/61 , H04N19/625 , H04N19/91 , H04N7/32
摘要： PURPOSE: To avoid access contention to a frame memory by using the decoder as part of a coder and setting freely a delay time. CONSTITUTION: The decoder is provided with an output terminal LO2 used to output reference image information read from a frame memory 34 to a delay circuit 40 provided externally and an input terminal L13 used to input image information via the delay circuit 40 to be added to inversely quantized image information, a delay circuit with a fixed delay time not required for the decoder is not mounted and a change in a processing time required for quantization is processed flexibly. Furthermore, a buffer memory storing tentatively the inversely quantized image information and the reference image information is provided to adjust a write access time of the frame memory thereby avoiding contention with a read access time.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式