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1. 发明专利

JP2008165449A Error correction code generation method and memory control device 有权
标题翻译：错误校正代码生成方法和存储器控制器件
公开(公告)号：JP2008165449A
公开(公告)日：2008-07-17
申请号：JP2006353505
申请日：2006-12-27
申请人： Fujitsu Ltd , 富士通株式会社
发明人： HIRANO TAKAHITO , MIURA TAKASHI , YAMAZAKI IWAO
IPC分类号： G06F12/08 , G06F12/16
CPC分类号： G06F11/1064 , G11C2029/0411
摘要： PROBLEM TO BE SOLVED: To generate a correct error correction code even when any RAM error occurs before storage data are actually written in a cache memory(RAM) after confirming that there is no error in cache line data to be stored. SOLUTION: The cache line data to be stored are stored in a register before writing the storage data, and the storage data are written in a cache memory, and the register storage content and the store data are merged, and an error correction code is generated with respect to the merge result. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：即使在存储数据被实际写入高速缓存存储器（RAM）中之后，即使在存储数据没有错误的高速缓存行数据中没有发生任何RAM错误发生时，也可以生成正确的纠错码。解决方案：在写入存储数据之前，要存储的高速缓存行数据被存储在寄存器中，并且将存储数据写入高速缓存存储器中，并且将存储器存储内容和存储数据合并，并进行纠错相对于合并结果生成代码。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2004038339A Data processor and aligning method for storage data 有权
公开(公告)号：JP2004038339A
公开(公告)日：2004-02-05
申请号：JP2002191443
申请日：2002-06-28
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MIURA TAKASHI , YAMAZAKI IWAO
IPC分类号： G06F9/30 , G06F9/315 , G06F9/38 , G06F12/00 , G06F12/08
CPC分类号： G06F9/30032 , G06F9/30025 , G06F9/3824 , G06F12/0886
摘要： PROBLEM TO BE SOLVED: To simplify the configuration of an aligning circuit provided in the pre-stage of a cache memory. SOLUTION: An arithmetic part 11 performs an arithmetic operation according to an instruction, and outputs data obtained as the result of the arithmetic operation. Data outputted from the arithmetic part 11 are stored in a store buffer 13. The data read from the store buffer 13 are stored in a cache memory 16. The aligning circuit 12 is made to rearrange the data outputted from the arithmetic part 11, and stored in the store buffer 13, and the aligning circuit 15 is made to rearrange the data read from the store buffer 13, and stored in the cache memory 16. Thus, it is possible to reduce a workload for rearranging the data in the align circuit 15. COPYRIGHT: (C)2004,JPO

3. 发明专利

JP2014112360A Arithmetic processing unit and control method of arithmetic processing unit 有权
标题翻译：算术处理单元和算术处理单元的控制方法
公开(公告)号：JP2014112360A
公开(公告)日：2014-06-19
申请号：JP2013220675
申请日：2013-10-23
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MIURA TAKASHI
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/0888
摘要： PROBLEM TO BE SOLVED: To provide an arithmetic processing unit capable of effectively issuing a non-cache request.SOLUTION: An arithmetic processing unit includes: a first controller controlling cache memory; and a second controller to which a non-cache space accessed not through the cache memory is allocated. If conditions that a processing order of a first or second access request to the non-cache space is allowed to overtake each other and that access destinations of the first and second access requests are identical are satisfied, the first controller issues the second access request to the second controller, without waiting for a completion notice from the second controller with regard to the first access request previously issued to the second controller. If the conditions are not satisfied, the first controller waits for a completion notice from the second controller with regard to the first access request previously issued to the second controller, before issuing the second access request to the second controller.
摘要翻译：要解决的问题：提供一种能够有效地发出非高速缓存请求的运算处理单元。解算：算术处理单元包括：控制高速缓冲存储器的第一控制器; 以及分配不通过高速缓冲存储器访问非缓存空间的第二控制器。如果允许对非高速缓存空间的第一或第二访问请求的处理顺序被允许超越并且第一和第二访问请求的访问目的地相同的条件满足，则第一控制器向第第二控制器，而不用等待来自第二控制器的关于先前发给第二控制器的第一访问请求的完成通知。如果条件不满足，则在向第二控制器发出第二访问请求之前，第一控制器等待来自第二控制器的关于先前发给第二控制器的第一访问请求的完成通知。

4. 发明专利

JP2006040143A Information processor and store instruction control method 有权
标题翻译：信息处理器和存储指令控制方法
公开(公告)号：JP2006040143A
公开(公告)日：2006-02-09
申请号：JP2004222044
申请日：2004-07-29
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MIURA TAKASHI , YAMAZAKI IWAO
IPC分类号： G06F9/38 , G06F12/00 , G06F12/08
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3826 , G06F9/3834 , G06F9/3842 , G06F9/3861
摘要： PROBLEM TO BE SOLVED: To enhance use efficiency of an arithmetic register which holds store data when a store instruction to store data in a predetermined storage area on a main memory or on a cache memory is executed. SOLUTION: This information processor is constituted so that an instruction processing part 10 issues, when the arithmetic register 22 in which an arithmetic result is held is established, an arithmetic result from the arithmetic register 22 to store data buffers 50-0 to 50-n as store data and is provided with a suppressing part 82 which suppresses setting of a store data holding flag 30d to an off state by a reset part 81 at the point of time when the store instruction is held in store ports 30-0 to 30-n and maintains an on state of the store data holding flag 30d when the store data are held in the store data buffers 50-0 to 50-n before the store instruction is held in the store ports 30-0 to 30-n. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：当执行在主存储器或高速缓冲存储器上的预定存储区域中存储数据的存储指令时，提高保存存储数据的算术寄存器的使用效率。解决方案：该信息处理器被构造成使得指令处理部分10在其中保存算术结果的算术寄存器22被建立时发出来自算术寄存器22的算术结果，以将数据缓冲器50-0存储到 50-n作为存储数据，并且设置有抑制部分82，其抑制在存储指令被保存在存储端口30-0中的时间点处由复位部分81将存储数据保持标志30d设置为关闭状态当将存储数据保存在存储数据缓冲器50-0至50-n中之前，存储数据保持标志30d保持在存储指令30-0至30- ñ。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JPH05174691A SEESAW BALANCE TYPE POLARIZED RELAY 失效
公开(公告)号：JPH05174691A
公开(公告)日：1993-07-13
申请号：JP34418191
申请日：1991-12-26
申请人： FUJITSU LTD
发明人： SATO SHINICHI , MIURA TAKASHI , OKAMOTO YOSHIO , TANAKA TAKANORI
IPC分类号： H01H50/36 , H01H50/18 , H01H51/24
摘要： PURPOSE:To simplify a structure, and also reduce electric power consumption by shifting a load of an armature composed of a movable contact point spring and a suction force generated by a permanent magnet in the direction for being strengthened on the normal open side, and sucking the edge part of the armature by means of an open side magnetic pole part even if a magnetic flux generated by a coil is small. CONSTITUTION:Though a movable contact point spring 1 and an armature 2 are formed integrally in the central part through an insulating body 6 so as to become parallel with each other, a support part 11 is twisted to the spring 1, so that a plane containing the support part 11 and a plane containing the spring 1 can cross each other when seen from the side surface. When seen from the side surface in an electric current unimpressed condition after the spring 1 is installed in a box body in this way, the support part 11 is supported with the box body, so that a plane containing the edge surfaces of magnetic pole parts 31 and 32 and a plane opposed to the magnetic pole parts 31 and 32 of the armature 2 can be expanded in one direction. Thereby, a suction force of the magnetic pole parts 31 and 32 generated by a permanent magnet 7 becomes asymmetrical between left and right as shown by a broken line, so that the suction force generated by the open side magnetic pole part 32 can be shifted in the direction for becoming larger than the suction force generated by the closed side magnetic pole part 31.

6. 发明专利

JPH05174684A LOW OPERATING SOUND TYPE ELECTROMAGNETIC RELAY 失效
公开(公告)号：JPH05174684A
公开(公告)日：1993-07-13
申请号：JP33539091
申请日：1991-12-19
申请人： FUJITSU LTD
发明人： IKEDA KEIJI , MIURA TAKASHI , UCHINO HIROYUKI
IPC分类号： H01H50/30
摘要： PURPOSE:To improve a quality, and also increase the range of its use by reducing respectively a collision sound of a contact shoe and a head part of an iron core generating when an electromagnetic relay is operated and a collision sound of the contact shoe and a movable spring generating when an operations is restored to the original state. CONSTITUTION:A shock absorbing member 9 is arranged protrusively in the tip part of an armature 3 where a head part of an iron core 1b and a movable spring 4 are opposed to each other. This member 9 is fitted in/fixed to an installation hole 3a arranged in the armature 3 thinned by forming step parts on the upper surface of the tip part, and the upper surface is protruded so as to be flush with thickness of the armature 3, and the lower edge is protruded so that the armature 3 does not butt the head part of the iron core 1b. Isoprene rubber, chroprene rubber, silicon rubber, and so on are used in the member 9, and the movable spring 4 is also constructed between a yoke 2 and the armature 3, so that the armature 3 is energized so as to separate always from the head part of the iron core 1b. The tip part of the spring 4 is further formed in a movable contact point 4a, so that at least one part can be brought into contact elastically with a fixed contact point 5 when an operation is restored to the original state.

7. 发明专利

JPH04264321A POLARIZED ELECTROMAGNETIC RELAY 失效
公开(公告)号：JPH04264321A
公开(公告)日：1992-09-21
申请号：JP2430991
申请日：1991-02-19
申请人： FUJITSU LTD
发明人： SATO SHINICHI , MIURA TAKASHI , OKAMOTO YOSHIO , TANAKA TAKANORI
IPC分类号： H01H50/16 , H01H51/24
摘要： PURPOSE:To improve a polarized electromagnetic relay in withstand voltage property. CONSTITUTION:A polarized electromagnetic relay consists of an electromagnetic coil 3, a U-shaped yoke 4 passing through the electromagnetic coil 3, a permanent magnet 5 extended along one side of the electromagnetic coil 3 with one end connected to one end of the yoke 4 and the other end connected to the other end of the yoke 4, an armature 6 extended along the permanent magnet 5 with one end opposed to one magnetic pole of the yoke 4 and the other end opposed to the other magnetic pole of the yoke 4 in an oscillatable manner, an insulation sheet 22 inserted between the electromagnetic coil 3 and the permanent magnet 5. The insulation sheet 22 is wider than either the electromagnetic coil 3 or the permanent magnet 5. The insulation sheet 22 is longer than the electromagnetic coil 3.

8. 发明专利

JPH04174929A ELECTROMAGNETIC RELAY 失效
公开(公告)号：JPH04174929A
公开(公告)日：1992-06-23
申请号：JP30171490
申请日：1990-11-07
申请人： FUJITSU LTD
发明人： ENDO TOMOHISA , MIURA TAKASHI , OKAMOTO YOSHIO , TANAKA TAKANORI , SATO SHINICHI
IPC分类号： H01H50/18 , H01H51/24
摘要： PURPOSE:To simplify the shape or working means to improve productivity by a method wherein positioning is made by making a projection formed by press-working in a plate-like armature equipped with movalbe springs contact with a flat-plate-like permanent magnet of electromagnet. CONSTITUTION:An electromagnetic relay is equipped with a U-shaped yoke 21, an electromagnet 6 having a magnetic circuit made up of a permanent magnet 61 installed between both ends of a coil 22 wound round the center of the yoke 21 and the yoke 21, an armature 71 which comes in contact only with the cross direction of the center in the longitudinal direction with the surface of the magnet 61 and moves like a seesaw relative to the magnet 61, and a contact spring set 7 having movable springs 73a, 73b which are insulatedly fixed to the armature 71 and always come into contact with common terminals 81a, 81b. A movable mold 72 in which the springs 73a, 73b are insertion-molded is equipped with trapezoidal notches 73a, 73b which are made to agree with upper projections 82a4, 82b4 of the terminals 81a, 81b to position the spring set 7 relative to the electromagnet 6 while the spring set 7 is circularly moved like a seesaw to change over the circuit.

9. 发明专利

JPS6394523A DRIVING CIRCUIT FOR LATCHING RELAY 失效
公开(公告)号：JPS6394523A
公开(公告)日：1988-04-25
申请号：JP23873086
申请日：1986-10-07
申请人： FUJITSU LTD
发明人： NAKAMURA AKIHIKO , MIURA TAKASHI
IPC分类号： H01H47/22 , H01H47/32

10. 发明专利

JPS6393214A SET/RESET CIRCUIT FOR FLIP FLOP 失效
公开(公告)号：JPS6393214A
公开(公告)日：1988-04-23
申请号：JP23872986
申请日：1986-10-07
申请人： FUJITSU LTD
发明人： NAKAMURA AKIHIKO , MIURA TAKASHI , TANAKA SHINICHI
IPC分类号： H03K3/037
摘要： PURPOSE:To eliminate signal delay and to facilitate detecting the position where trouble occurs, by combining two NAND circuits and AND circuits in the circuit whose set or reset are determined at the time of power-on in accordance with application of the signal in the high level or the low level to a state determining signal terminal. CONSTITUTION:Two NAND circuits 21 and 22 and two AND circuits 23 and 24 are provided, and a voltage obtained by integrating a supply voltage 5 by a resistance 12 and a capacitor 13 is applied to one terminal of each of circuits 21 and 22, and the other terminals are connected to input and output terminals of an inverter 9 for a signal terminal 2 of the signal which determines the state of a flip flop FF 1, and one terminal of the circuit 23 and that of the circuit 24 are connected to a reset terminal 3 and a set terminal 4, and the other terminals are connected to output terminals of circuits 21 and 22 and respective output terminals of AND circuits are individually connected to the set terminal and the reset terminal of the FF 1. Thus, the signal applied to the terminal 2 is immediately operated by the combinational circuit of AND circuits and NAND circuits to determine the state of the FF 1 as an automatic reset circuit or an automatic set circuit. Therefore, the signal propagation time is shortened. The position where trouble occurs is easily detected because of the simple constitution.

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