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1. 发明专利

JP2012216835A Method of patterning gate stack of non-volatile memory with formation of capacitor 有权
标题翻译：用于形成电容器的非易失性存储器的栅极堆栈的方法
公开(公告)号：JP2012216835A
公开(公告)日：2012-11-08
申请号：JP2012081775
申请日：2012-03-30
申请人： Freescale Semiconductor Inc , フリースケールセミコンダクターインコーポレイテッド
发明人： SMITH BRADLEY P , MEHUL D SHROFF
IPC分类号： H01L27/115 , H01L21/336 , H01L21/822 , H01L21/8247 , H01L27/04 , H01L27/10 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L21/28273 , H01L28/60
摘要： PROBLEM TO BE SOLVED: To form a capacitor and an NVM cell in an integrated fashion so that etching of the capacitor is useful in end point detection of etching of the NVM cell.SOLUTION: The purpose of the invention is achieved using two conductive layers over an NVM region and over a capacitor region. A first conductive layer is patterned in preparation for a subsequent patterning step which includes a step of patterning both the first conductive layer and the second conductive layer in both the NVM region and the capacitor region. Subsequent etching provides an important alignment of a floating gate onto a control gate by having both conductive layers etched using the same mask. During this subsequent etching, the fact that first conductive material is being etched in the capacitor region helps end point detection of the etching of the first conductive layer in the NVM region.
摘要翻译：要解决的问题：以集成方式形成电容器和NVM单元，使得电容器的蚀刻对于NVM单元的蚀刻的端点检测是有用的。解决方案：本发明的目的是通过NVM区域和电容器区域上的两个导电层来实现的。对第一导电层进行图案化以制备随后的图案化步骤，其包括在NVM区域和电容器区域中图案化第一导电层和第二导电层的步骤。随后的蚀刻通过使用相同的掩模蚀刻两个导电层来提供浮动栅极到控制栅极的重要对准。在该后续蚀刻期间，第一导电材料在电容器区域中被蚀刻的事实有助于终端检测NVM区域中的第一导电层的蚀刻。版权所有（C）2013，JPO＆INPIT

2. 发明专利

JP2013046061A Injection for enhancing performance of selected transistor in integrated circuit 审中-公开
标题翻译：注意增强集成电路中选择的晶体管的性能
公开(公告)号：JP2013046061A
公开(公告)日：2013-03-04
申请号：JP2012169552
申请日：2012-07-31
申请人： Freescale Semiconductor Inc , フリースケールセミコンダクターインコーポレイテッド
发明人： MEHUL D SHROFF , WILLIAM F JOHNSTONE , CHAD E WEINTRAUB
IPC分类号： H01L21/8234 , H01L27/088
CPC分类号： H01L27/088 , H01L21/823412 , H01L21/823493 , H01L27/0207
摘要： PROBLEM TO BE SOLVED: To alter the characteristics of a transistor to more desirable characteristics, without replacing all or some mask sets.SOLUTION: A well for forming multiple transistors is formed by performing first injection on a substrate. Each transistor in first subset out of the multiple transistors thus formed has a width satisfying a predetermined width limitation, and each transistor in second subset has a width not satisfying a predetermined width limitation. Second injection is performed not in a region of a well where the transistors of second subset are formed, but in a region of a well where the transistors of first subset are formed. Transistors are formed, and the channel region of each transistor of first subset is formed in a part of a substrate received the second injection, whereas the channel region of each transistor of second subset is formed in a part of a substrate not received the second injection.
摘要翻译：要解决的问题：为了将晶体管的特性改为更理想的特性，而不需要更换所有或一些掩模组。解决方案：通过在衬底上执行第一次注入来形成用于形成多个晶体管的阱。如此形成的多个晶体管中的第一子集中的每个晶体管具有满足预定宽度限制的宽度，并且第二子集中的每个晶体管具有不满足预定宽度限制的宽度。不是在形成第二子集的晶体管的阱的区域中，而是在形成第一子集的晶体管的阱的区域中进行第二次注入。形成晶体管，并且第一子集的每个晶体管的沟道区形成在接收第二注入的衬底的一部分中，而第二子集的每个晶体管的沟道区形成在未接收第二注入的衬底的一部分中。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2013120937A Method and structure for protection against via failure 审中-公开
标题翻译：通过失败保护的方法和结构
公开(公告)号：JP2013120937A
公开(公告)日：2013-06-17
申请号：JP2012259248
申请日：2012-11-28
申请人： Freescale Semiconductor Inc , フリースケールセミコンダクターインコーポレイテッド
发明人： MEHUL D SHROFF , DOUGLAS M REBER , EDWARD O TRAVIS
IPC分类号： H01L21/82 , H01L21/768
CPC分类号： H01L23/522 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a method for forming a decoy via and a functional via.SOLUTION: Provided is a semiconductor device comprising: a first interconnect layer having a plurality of metal portions including a first metal portion; a second interconnect layer having plurality of metal portions including a second metal portion; a third interconnect layer having a plurality of metal portions including a third metal portion; a functional via coupled to the first metal portion and the second metal portion; and a decoy via in a protection region around the functional via, the decoy via coupled to the first metal portion and the third metal portion.
摘要翻译：要解决的问题：提供一种用于形成诱饵通孔和功能通孔的方法。解决方案：提供一种半导体器件，包括：第一互连层，具有包括第一金属部分的多个金属部分; 第二互连层，具有包括第二金属部分的多个金属部分; 第三互连层，具有包括第三金属部分的多个金属部分; 耦合到所述第一金属部分和所述第二金属部分的功能通路; 以及在功能通孔周围的保护区域中的诱饵通道，所述诱饵通孔联接到第一金属部分和第三金属部分。版权所有（C）2013，JPO＆INPIT

4. 发明专利

JP2014175666A Process for integration using thermal oxide select gate dielectric for select gate and partial replacement gate for logic 有权
标题翻译：使用热氧选择栅电介质进行选择栅的集成处理和部分逻辑替换门
公开(公告)号：JP2014175666A
公开(公告)日：2014-09-22
申请号：JP2014045274
申请日：2014-03-07
申请人： Freescale Semiconductor Inc , フリースケールセミコンダクターインコーポレイテッド
发明人： HALL MARK D , MEHUL D SHROFF , FRANK K BAKER JR
IPC分类号： H01L27/115 , H01L21/336 , H01L21/8247 , H01L27/10 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66545 , H01L27/11534 , H01L29/66825
摘要： PROBLEM TO BE SOLVED: To provide a method of making a logic transistor in a logic region and a non-volatile memory cell in a non-volatile memory region of the same substrate.SOLUTION: A thermally-grown oxygen-containing layer is formed over a control gate in a non-volatile memory region, and a high-k gate dielectric layer and barrier layer are formed in a logic region. A polysilicon layer is formed over the oxygen-containing layer and barrier layer and is planarized. A first masking layer is formed over the polysilicon layer and control gate defining a select gate location adjacent to the control gate. A second masking layer is formed defining a logic gate location. Exposed portions of the polysilicon layer are removed such that a select gate remains at the select gate location and a polysilicon portion remains at the logic gate location. A dielectric layer is formed around the select and control gates and polysilicon portion. The polysilicon portion is removed to result in an opening at the logic gate location which exposes the barrier layer.
摘要翻译：要解决的问题：提供在同一衬底的非易失性存储器区域中的逻辑区域和非易失性存储器单元中制造逻辑晶体管的方法。解决方案：将热生长的含氧层形成在在非易失性存储区域中的控制栅极和高k栅极电介质层和阻挡层形成在逻辑区域中。在含氧层和阻挡层上方形成多晶硅层并进行平坦化。第一掩模层形成在多晶硅层上，控制栅极限定与控制栅极相邻的选择栅极位置。形成定义逻辑门位置的第二掩蔽层。去除多晶硅层的暴露部分，使得选择栅极保留在选择栅极位置处，并且多晶硅部分保持在逻辑门位置。在选择和控制栅极和多晶硅部分周围形成介电层。去除多晶硅部分以在逻辑门位置处产生暴露阻挡层的开口。

5. 发明专利

JP2014086724A Method of making logic transistor and non-volatile memory (nvm) cell 审中-公开
标题翻译：制造逻辑晶体管和非易失性存储器（NVM）单元的方法
公开(公告)号：JP2014086724A
公开(公告)日：2014-05-12
申请号：JP2013199780
申请日：2013-09-26
申请人： Freescale Semiconductor Inc , フリースケールセミコンダクターインコーポレイテッド
发明人： MEHUL D SHROFF , HALL MARK D , FRANK K BAKER JR
IPC分类号： H01L27/115 , H01L21/336 , H01L21/8247 , H01L27/10 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28273 , H01L21/28282 , H01L27/11534 , H01L27/11536 , H01L27/11573 , H01L29/66545
摘要： PROBLEM TO BE SOLVED: To provide a method of making a logic transistor and a non-volatile memory (NVM) cell.SOLUTION: An oxide-containing layer is formed directly on a semiconductor layer in an NVM region (14), and a first partial layer of a first material is formed over the oxide-containing layer in the NVM region. A first high-K dielectric layer is formed directly on the semiconductor layer in a logic region (16). A first conductive layer is formed over the first dielectric layer in the logic region. A second partial layer of the first material is formed directly on the first partial layer in the NVM region and over the first conductive layer in the logic region. A logic device is formed in the logic region. An NVM cell is formed in the NVM region, and the first and second partial layers together are used to form one of a charge storage layer if the cell is a floating gate cell or a select gate if the cell is a split gate cell.
摘要翻译：要解决的问题：提供制造逻辑晶体管和非易失性存储器（NVM）单元的方法。解决方案：在NVM区域（14）中的半导体层上直接形成含氧化物层，第一在NVM区域中的含氧化物层上形成第一材料的部分层。第一高K电介质层直接形成在逻辑区域（16）中的半导体层上。第一导电层形成在逻辑区域中的第一介电层上。第一材料的第二部分层直接形成在NVM区域中的第一部分层上并且在逻辑区域中的第一导电层上方形成。在逻辑区域中形成逻辑器件。在NVM区域中形成NVM单元，并且如果单元是浮动栅极单元或单元是分离栅极单元，则第一和第二部分层一起用于形成电荷存储层之一。

6. 发明专利

JP2013058753A Incident capacitive sensor 审中-公开
标题翻译：偶发电容式传感器
公开(公告)号：JP2013058753A
公开(公告)日：2013-03-28
申请号：JP2012195705
申请日：2012-09-06
申请人： Freescale Semiconductor Inc , フリースケールセミコンダクターインコーポレイテッド
发明人： MARK D HALL , MEHUL D SHROFF
IPC分类号： H01L31/00 , G01T1/24 , H01L31/09
CPC分类号： H01L31/119 , G01J5/34 , G01S3/783 , G01T1/24 , H01L31/02327 , H01L31/113
摘要： PROBLEM TO BE SOLVED: To provide a capacitive sensor device for measuring radiation.SOLUTION: The device includes two sensor regions and a top plate structure. The sensor regions are made of a material that generates electron-hole pairs when radiation strikes the material. A separation region is located between the two sensor regions. The capacitance between a sensor region and the top plate is dependent upon radiation striking the sensor region. A blocking structure selectively and differentially blocks radiation having a parameter value in some range from the sensor region so as to differentially impact electron-hole pair generation in one sensor region with respect to electron-hole pair generation in the other sensor region at selected angles of incidence of the radiation.
摘要翻译：要解决的问题：提供用于测量辐射的电容式传感器装置。
解决方案：该装置包括两个传感器区域和顶板结构。传感器区域由辐射冲击材料时产生电子 - 空穴对的材料制成。分离区域位于两个传感器区域之间。传感器区域和顶板之间的电容取决于辐射到传感器区域。阻挡结构选择性地并且有差别地阻挡从传感器区域在一定范围内的参数值的辐射，以便在一个传感器区域中相对于另一传感器区域中的电子 - 空穴对产生的电子 - 空穴对产生在选定的角度辐射的发生率。版权所有（C）2013，JPO＆INPIT

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