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1. 发明专利

JP2002237804A DIGITAL SUBSCRIBER'S LINE TRANSMISSION METHOD, TRANSMISSION DEVICE, AND TRANSMISSION SYSTEM 失效
公开(公告)号：JP2002237804A
公开(公告)日：2002-08-23
申请号：JP2000146531
申请日：2000-05-18
申请人： FUJITSU LTD
发明人： HASEGAWA KAZUTOMO , ASAHINA SHUGO , MIYOSHI SEIJI , KOIZUMI NOBUKAZU , AWATA YUTAKA
IPC分类号： H04L5/16 , H04B1/38 , H04B1/56 , H04B3/02 , H04B3/10 , H04B3/20 , H04B3/32 , H04J1/12 , H04J1/16 , H04J11/00 , H04L5/02 , H04L5/14 , H04L25/03 , H04L27/26 , H04L29/06 , H04M11/06 , H04Q11/04
摘要： PROBLEM TO BE SOLVED: To prevent waveform distortion from occurring in the leading symbol of a burst symbol train and to protect a subscriber's circuit against crosstalk caused by an adjacent circuit. SOLUTION: In a digital subscriber's line transmission (xDSL), the partial data 503 and 504 of a training symbol train are added in front and/or in back of the burst symbol train 502 for transmission, so as to prevent waveform distortion from occurring in the leading symbol 501 of a burst symbol train 502 at a training symbol transmitting end when training is carried out prior to data communication. Data added to the training symbol train are removed at a receiving end, and a training process is executed. The training symbol train and a transmission symbol train in normal transmission are set to have lengths not to be affected by NEXT (near crosstalk) caused by adjacent circuits.

2. 发明专利

JPH0951329A TIMING REPRODUCTION CIRCUIT 失效
公开(公告)号：JPH0951329A
公开(公告)日：1997-02-18
申请号：JP19783195
申请日：1995-08-02
申请人： FUJITSU LTD
发明人： KOIZUMI NOBUKAZU , AWATA YUTAKA , MIYOSHI SEIJI , OOTOMO YASUHISA
IPC分类号： H04L25/03 , H04B3/06 , H04L7/00 , H04L7/027
摘要： PROBLEM TO BE SOLVED: To use a timing reproduction circuit for the digital transmission devices of a station-side and a subscriber-side and to suppress the circuit scale to be a minimum. SOLUTION: In the timing reproduction circuit 3 which is used for the digital transmission device 1 provided with an identification circuit 2 and which is provided with a frequency error detection part 31, a phase deviation detection part 32 and a timing reproduction part 33, the frequency error detection part 31 is provided with a first detection stop circuit 311 which can stop the detection of a frequency error component in accordance with the presence or absence of the frequency error component of a reception signal. The timing reproduction part 33 is constituted to reproduce signal identification timing based on phase deviation information from the phase deviation detection part 32 when the detection of the frequency error component in the frequency error detection part 31 is stopped by the first detection stop circuit 311.

3. 发明专利

JPH07162343A METHOD FOR UPDATING TAP COEFFICIENT FOR ADAPTIVE FILTER 失效
公开(公告)号：JPH07162343A
公开(公告)日：1995-06-23
申请号：JP30211093
申请日：1993-12-02
申请人： FUJITSU LTD
发明人： KOIZUMI NOBUKAZU , AWATA YUTAKA
IPC分类号： H04B3/23
摘要： PURPOSE:To provide an adaptive filter tap coefficient updating method capable of reducing the power consumption of a tap coefficient updating circuit. CONSTITUTION:The signs of sign (ai), sign (ai+1),..., sign (ai+m-1) of tap data at an m sampling period (m is an integer >2) are found out, the signs of sign (epsilon0), sign (epsilon1),..., sign (epsilonm-1) of residual errors at the m sampling period are found out, the product of sign (ai+k-1) * sign (epsilonk-1) of the tap data sign (ai+k-1) at the m sampling period and the residual error sign (epsilonk-1) at the m sampling period is added from k=1 to k=m, and an added result is multiplied by a control coefficient in each m sampling period to obtain the updated value of the tap coefficient.

4. 发明专利

JPH04245809A DECISION FEEDBACK TYPE EQUALIZER 失效
公开(公告)号：JPH04245809A
公开(公告)日：1992-09-02
申请号：JP2901991
申请日：1991-01-31
申请人： FUJITSU LTD
发明人： AWATA YUTAKA , KOIZUMI NOBUKAZU
IPC分类号： H04B3/10 , H03H15/00 , H03H17/00 , H03H21/00
摘要： PURPOSE:To speed up the convergence of a tap coefficient and a sampling phase in respect of a decision feedback type equalizer to equalize a received signal given inter-symbol interference due to transmission distortion. CONSTITUTION:A tap coefficient updating part 4 which updates and controls the tap coefficient so that an error signal between the decision output signal of a deciding part 1 and an equalization signal is decreased, updates and controls only the tap coefficient of a main cursor at the time of initial pull-in, and stops the update and control of the tap coefficient of a pre-cursor for forming a timing signal and the tap coefficient of a post cursor for forming a false inter-symbol interference signal R1 by a delay circuit 2, a coefficient multiplier 3 and an adding part 5, and after the tap coefficient of the main cursor approaches to an optimum value, it executes the update and control of all tap coefficients.

5. 发明专利

JPH03184437A TIMING REGENERATION CIRCUIT 失效
公开(公告)号：JPH03184437A
公开(公告)日：1991-08-12
申请号：JP32265389
申请日：1989-12-14
申请人： FUJITSU LTD
发明人： AWATA YUTAKA , OTA SHINJI , KUGIMIYA JUNICHI
IPC分类号： H04L7/00
摘要： PURPOSE:To accurately find a timing phase by smoothing an impulse response string receiving the influence of inter-code interference at a low-pass filter means. CONSTITUTION:An evaluation function arithmetic part 14 shifts the timing of sampling at a prescribed interval for one signal duration, and performs the calculation of respective sampling timing corresponding to an impulse response from the sample value fk and the digital identification value ak of a reception signal from past to the present within constant time, and stores the string of impulse response obtained at plural sampling timing. A filter arithmetic part 15 realizes the function of the low-pass filter means 6, and smoothes the above stated string of impulse response. A maximum value phase decision means 9 decides the sampling timing which supplies the maximum value of the smoothed string of impulse response as the optimum timing phase for the reception signal.

6. 发明专利

JPH02222206A LINE EQUALIZER 失效
公开(公告)号：JPH02222206A
公开(公告)日：1990-09-05
申请号：JP4243489
申请日：1989-02-22
申请人： FUJITSU LTD
发明人： KAWADA KINJI , AWATA YUTAKA , TOKIWA KOJI , KUGIMIYA JUNICHI , MARUYAMA KAZUYOSHI
IPC分类号： H03G3/30
摘要： PURPOSE:To avoid useless power operation time with respect to an input signal with an excess or deficient amplitude by discriminating the quantity of the input signal level from the amplitude and applying the processing in parallel with the power operation. CONSTITUTION:A comparator section 5 decided whether an amplitude of an input waveform is within a normal range larger than the minimum amplitude not including a quantizing error and smaller than a maximum amplitude not saturated from the output of an A/D converter 2 and informs the result to a gain control section 4. The gain control section 4 adjusts the gain of an equalizer 1 quantitatively immediately without awaiting the arrival of an output of a power calculation section 3 when the output of a comparator section 5 is at the outside of the normal range. Thus, no useless power operation with respect to an input of an excess or deficient amplitude is applied to set the gain of an eualizer.

7. 发明专利

JPH01307322A ECHO CANCELLER 失效
公开(公告)号：JPH01307322A
公开(公告)日：1989-12-12
申请号：JP13744188
申请日：1988-06-06
申请人： FUJITSU LTD
发明人： AWATA YUTAKA , KAWADA KINJI , YAMATO SEIICHI
IPC分类号： H04B3/23 , H03H21/00
摘要： PURPOSE:To attain the initial training of an echo canceller at the post stage simply by applying convolution calculation to each tap coefficient with an equalizer and an echo canceller of the pre-stage (1st) so as to use the coefficient as the tap coefficient of the post stage (2nd) of the equalizer. CONSTITUTION:First and second echo cancellers 8, 10 generate a pseudo echo signal based on a transmission data to cancel the echo in the reception signal and an equalizer 9 compensates the line loss. Then a convolution arithmetic section 11 is provided, which applies convolution calculation of each tap coefficient of the 1st echo canceller 8 and the equalizer 9 and the result of calculation obtained from it is outputted to the 2nd echo canceller 10 as the tap coefficient. Thus, the initial training of the 2nd echo canceller 10 is simplified.

8. 发明专利

JPH0155770B2 失效
公开(公告)号：JPH0155770B2
公开(公告)日：1989-11-27
申请号：JP18937383
申请日：1983-10-12
申请人： FUJITSU LTD
发明人： UENO NORIO , AWATA YUTAKA , HINO YOJI
IPC分类号： H03F3/345 , H03F1/30 , H03F3/34 , H03F3/347

9. 发明专利

JPH01241926A SAMPLING CLOCK PHASE ADJUSTMENT SYSTEM 失效
公开(公告)号：JPH01241926A
公开(公告)日：1989-09-26
申请号：JP6875588
申请日：1988-03-23
申请人： FUJITSU LTD
发明人： AWATA YUTAKA , KAWADA KINJI , TOKIWA KOJI , YAMATO SEIICHI , KUGIMIYA JUNICHI
IPC分类号： H04B3/06 , H04B3/23
摘要： PURPOSE:To reduce the scale of circuit without widening the dynamic range of a post-stage echo canceller by providing a delay equalizer, a delay quantity detection section and a sampling clock phase adjustment circuit and making the sampling point of an echo canceller of the pre-stage and the post stage coincident. CONSTITUTION:A conventional multi-stage constitution echo canceller is provided with a delay equalizer 8, a delay quantity detection section 9 and a phase adjustment circuit 10. The pre-stage echo canceller 4 cancels the echo from the transmission at the leading of the clock, since the line equalizer 6 has a gain, the remaining echo cancel of the pre-stage echo canceller 4 is amplified and appears as the input to the post-stage echo canceller 5. Since the phase of the clock is deviated by the phase adjustment circuit 10 by the delay detected by the delay detection section 9 in the post-stage echo canceller 5, the echo is cancelled by a slight echo cancel quantity by making the sampling point coincident. Thus, the absolute width of the dynamic range of the post-stage echo canceller 5 is not required to be wide and the circuit scale is reduced.

10. 发明专利

JPH01114126A BALANCE NETWORK SELECTING CIRCUIT 失效
公开(公告)号：JPH01114126A
公开(公告)日：1989-05-02
申请号：JP27136787
申请日：1987-10-27
申请人： FUJITSU LTD
发明人： KAWADA KINJI , AWATA YUTAKA , TOKIWA KOJI , YAMATO SEIICHI
IPC分类号： H04B3/03 , H04B3/23
摘要： PURPOSE:To obtain a selecting circuit decreasing bypass echo by obtaining a digital signal in response to the output of a comparator by a sequential comparating circuit to extract a digital signal of a balance network as a detoured echo. CONSTITUTION:Selectors 17, 22 are switched to select a signal of a terminal (a) at the time of initial training, a switch 23 is connected to the terminal (a) and an isolated pattern is supplied to a terminal 8. A 6-bit counter 4 counts an isolated pattern and a switch decoder 3 selects a resistor array of the balanced network 2 as resistors Ry1 and Rx1, Ry1 and Rx2, Ry1 and Rx3,... at each production of the isolated pattern. In selecting an optimum balanced network, the selectors 17, 22 are selected to a terminal (b) to bring the actual transmission state and the switch 23 is connected to the terminal (b). Then the echo is canceled by an echo canceller section 15.

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