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1. 发明专利

JP2011112411A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2011112411A
公开(公告)日：2011-06-09
申请号：JP2009266922
申请日：2009-11-25
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： KOYAMA TAKAHIRO , OKUMA SADAYUKI
IPC分类号： G01R31/28 , H01L21/82 , H01L21/822 , H01L27/04
CPC分类号： G01R31/2644 , G11C29/1201 , G11C29/26 , G11C29/48 , G11C2029/2602 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2224/05599 , H01L2224/48091 , H01L2224/4824 , H01L2224/49113 , H01L2224/49175 , H01L2224/85399 , H01L2225/06562 , H01L2225/06596 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01055 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device testing a plurality of built-in semiconductor chips in parallel by using only a part of data input/output terminals. SOLUTION: The semiconductor device is equipped with: a first semiconductor chip which is connected to a plurality of first data input/output terminals, has a first test circuit and a first storage, and produces a first test result with the first test circuit according to data output from the first storage, on the occasion of test operation; and a second semiconductor chip which is connected to a plurality of second data input/output terminals, has a second and third test circuits and a second storage, and on the occasion of the test operation, produces a second test result with the second test circuit according to data output from the second storage, produces a third test result with the third test circuit according to the second test result and the first test result supplied from the first test circuit of the first semiconductor chip, and outputs the third test result to a predetermined second data input/output terminal. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供通过仅使用一部分数据输入/输出端子来并行测试多个内置半导体芯片的半导体器件。解决方案：半导体器件配备有：连接到多个第一数据输入/输出端子的第一半导体芯片，具有第一测试电路和第一存储器，并且在第一测试中产生第一测试结果电路根据数据输出从第一个存储，在测试操作的场合; 以及连接到多个第二数据输入/输出端子的第二半导体芯片，具有第二和第三测试电路和第二存储器，并且在测试操作时，产生第二测试电路的第二测试结果根据第二存储器的数据输出，根据第二测试结果产生第三测试电路的第三测试结果和从第一半导体芯片的第一测试电路提供的第一测试结果，并将第三测试结果输出到预定的第二数据输入/输出端。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2010140531A Test method of multi-i/o semiconductor memory 审中-公开
标题翻译：多I / O半导体存储器的测试方法
公开(公告)号：JP2010140531A
公开(公告)日：2010-06-24
申请号：JP2008313819
申请日：2008-12-10
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： YAMAZAKI AKIO , OKUMA SADAYUKI
IPC分类号： G11C29/56 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide a test method which efficiently tests a multi-I/O semiconductor memory.
SOLUTION: The test method determines whether output data from each memory I/O is at the same output level and determines the quality of the semiconductor memory by using its output as a quality determination output. The semiconductor memory includes an exclusive OR gate provided in a front stage of an output data buffer of an input/output circuit and a latch circuit. When writing data, the latch circuit latches data inputted from a tester I/O pin as an expected value, and when reading data, the exclusive OR gate compares and determines whether the input data read from the inside of the semiconductor memory matches the expected value from the latch circuit, and outputs the result of determination from the output data buffer.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种有效测试多I / O半导体存储器的测试方法。
解决方案：测试方法确定来自每个存储器I / O的输出数据是否处于相同的输出电平，并通过使用其输出作为质量确定输出来确定半导体存储器的质量。半导体存储器包括设置在输入/输出电路和锁存电路的输出数据缓冲器的前级中的异或门。当写入数据时，锁存电路将从测试器I / O引脚输入的数据锁存为预期值，当读取数据时，异或门比较并确定从半导体存储器的内部读取的输入数据是否与期望值相匹配并从输出数据缓冲器输出确定结果。（C）2010，JPO＆INPIT

3. 发明专利

JP2013069393A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013069393A
公开(公告)日：2013-04-18
申请号：JP2011208954
申请日：2011-09-26
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： IWATA CHIHIRO , OKUMA SADAYUKI
IPC分类号： G11C29/14
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device including a test signal generating circuit for resetting a test circuit.SOLUTION: The semiconductor device comprises: test circuits (CKT1 to CKT4) for executing a test based on an activity-level test mode signal; a test signal generating circuit (106) for outputting an activity-level test mode signal (TMS) based on a test mode setting command; and a reset circuit (40) for maintaining the test mode signal from the test signal generating circuit at an inactive level, in a predetermined period of time after power supply, based on an effective signal (CKE) for enabling the operation of the semiconductor device to be input from the outside.
摘要翻译：要解决的问题：提供一种包括用于复位测试电路的测试信号发生电路的半导体器件。解决方案：半导体器件包括：用于基于活动级测试模式信号执行测试的测试电路（CKT1至CKT4）; 用于基于测试模式设置命令输出活动级测试模式信号（TMS）的测试信号产生电路（106）以及复位电路（40），用于在供电后的预定时间段内，基于用于使半导体器件的操作的有效信号（CKE），将来自测试信号发生电路的测试模式信号保持在非活动电平从外部输入。版权所有（C）2013，JPO＆INPIT

4. 发明专利

JP2013026960A Semiconductor device, timing detection method, and timing adjustment method 审中-公开
标题翻译：半导体器件，时序检测方法和时序调整方法
公开(公告)号：JP2013026960A
公开(公告)日：2013-02-04
申请号：JP2011162043
申请日：2011-07-25
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： OKUMA SADAYUKI
IPC分类号： H03K3/354 , G11C29/12 , G11C29/56
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device, a timing detection method, and a timing adjustment method that implement optimum timing detection and timing adjustment in terms of design values of the semiconductor device.SOLUTION: The semiconductor device includes: an oscillator circuit 1-2; a command circuit 1-1 for outputting to the oscillator circuit a test signal instructing the oscillator circuit to perform a clocking operation within an active period of the test signal; and a counter circuit 1-3 connected to the oscillator circuit to count up clocks by the clocking operation.

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