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1. 发明专利

JP2013118270A Method of manufacturing semiconductor device, and semiconductor device 有权
标题翻译：制造半导体器件的方法和半导体器件
公开(公告)号：JP2013118270A
公开(公告)日：2013-06-13
申请号：JP2011264732
申请日：2011-12-02
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： KIYOHARA TOSHINORI
IPC分类号： H01L23/50
CPC分类号： H01L2224/48091 , H01L2224/48247 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To reduce occurrence of erroneous determination in solder appearance inspection after a semiconductor device is mounted.SOLUTION: The method of manufacturing a semiconductor device includes a step of forming a step surface (half-punching region 25) oriented to a tip end side of a lead 20 on a mounting surface side of the lead 20 by half-punching the lead 20 of the semiconductor device 100 from the mounting surface side of the semiconductor device 100 toward an opposite surface thereof. The manufacturing method further includes steps of: forming a plating film 30 that covers the lead 20; and removing a portion on a tip end side beyond the step surface of the lead 20 by cutting the lead 20 along the extension surface of the step surface. The manufacturing method further includes a step of rolling out the plating film 30 on the surface opposite to the mounting surface of the lead 20 toward the tip end surface side of the lead 20.
摘要翻译：要解决的问题：为了减少在安装半导体器件之后的焊料外观检查中的错误确定的发生。解决方案：半导体器件的制造方法包括以下步骤：通过半冲压形成在引线20的安装表面侧上定向到引线20的前端侧的台阶表面（半冲压区域25）半导体器件100的引线20从半导体器件100的安装表面侧朝向其相对表面。该制造方法还包括以下步骤：形成覆盖引线20的镀膜30; 并且通过沿着台阶表面的延伸表面切割引线20，将前端侧的部分移除超过引线20的台阶表面。该制造方法还包括在与引线20的安装面相反的表面上朝向引线20的前端面侧推出电镀膜30的步骤。（C）2013，JPO＆INPIT

2. 发明专利

JP2015008229A 半導体装置およびその製造方法有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2015008229A
公开(公告)日：2015-01-15
申请号：JP2013133174
申请日：2013-06-25
申请人：ルネサスエレクトロニクス株式会社 , Renesas Electronics Corp
发明人： YAMASHITA HISANORI , KIYOHARA TOSHINORI
IPC分类号： H01L25/04 , H01L21/60 , H01L23/50 , H01L25/18
CPC分类号： H01L23/49575 , H01F2019/085 , H01L21/565 , H01L23/3107 , H01L23/49503 , H01L23/4952 , H01L23/5227 , H01L23/645 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/78 , H01L24/83 , H01L24/85 , H01L24/92 , H01L24/97 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/0612 , H01L2224/06164 , H01L2224/27013 , H01L2224/29294 , H01L2224/29339 , H01L2224/32245 , H01L2224/45099 , H01L2224/45147 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/48257 , H01L2224/48464 , H01L2224/48477 , H01L2224/48479 , H01L2224/49175 , H01L2224/49177 , H01L2224/73265 , H01L2224/78301 , H01L2224/78705 , H01L2224/83192 , H01L2224/85051 , H01L2224/85181 , H01L2224/85205 , H01L2224/85986 , H01L2224/92247 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01028 , H01L2924/01033 , H01L2924/12041 , H01L2924/15747 , H01L2924/181 , H01L2924/19042 , H01L2924/19104 , H04L25/0266 , H01L2924/00012 , H01L2924/00 , H01L2224/4554
摘要：【課題】半導体装置の信頼性の向上を図る。【解決手段】半導体チップ11と半導体チップ21を有するSOP1において、チップ間のワイヤ接続で、ワイヤ群6のうちワイヤ群7に最も近接するワイヤ6aとワイヤ群7のうちワイヤ群6に最も近接するワイヤ7aとのワイヤ間距離Lは、ワイヤ群6内およびワイヤ群7内のいずれのワイヤ間距離よりも大きいことにより、絶縁耐圧を確保することができる。これにより、SOP1の信頼性の向上を図ることができる。【選択図】図1
摘要翻译：要解决的问题：提高半导体器件的可靠性。解决方案：在具有半导体芯片11和半导体芯片21的SOP1中，相对于芯片之间的线连接，线6a之间的线间距离L 线组7最接近导线组7，线组6最靠近导线组6的导线7a被设定为大于导线组6中的任何其它线间距离，并且在线组7，从而可以确保绝缘耐压。由此，可以提高SOP1的可靠性。

3. 发明专利

JP2012119413A Method for manufacturing lead frame and apparatus for manufacturing lead frame 审中-公开
标题翻译：制造引线框架的方法和制造引线框架的装置
公开(公告)号：JP2012119413A
公开(公告)日：2012-06-21
申请号：JP2010266173
申请日：2010-11-30
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： GAO WEI , KIYOHARA TOSHINORI
IPC分类号： H01L23/48
CPC分类号： H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/4903 , H01L2924/1305 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a technique for avoiding an excessive temperature rise in a lead part when a high current flows through the lead part.SOLUTION: A lead frame 12 including a header 2 (header part) on which a semiconductor chip 3 (semiconductor element) is mounted and gate leads 4 etc. (lead parts) electrically connected to the semiconductor chip 3 is manufactured by pressing of sheet metal 13 as follows. Specifically, punches 18 having tapered tip portions 18a are pressed against second regions 22 of the sheet metal 13 adjacent to first regions 21 corresponding to the gate leads 4 etc. to deform the metal in the second regions 22 toward the first regions 21, which causes the first regions 21 to bulge to form the gate leads 4 etc.
摘要翻译：要解决的问题：提供一种当高电流流过引线部分时避免引线部分过度升温的技术。解决方案：包括其上安装有半导体芯片3（半导体元件）的集管2（集管部分）和与半导体芯片3电连接的栅极引线4等（引线部分）的引线框架12通过压制的金属板13。具体而言，具有锥形尖端部分18a的冲头18被压靠在与栅极引线4等对应的第一区域21相邻的金属板13的第二区域22上，以将第二区域22中的金属变形成朝向第一区域21，这导致第一区域21凸起以形成门引线4等。版权所有（C）2012，JPO＆INPIT

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