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1. 发明专利

JP2006108755A Radio equipment and radio transmission/reception system using the radio equipment 审中-公开
标题翻译：使用无线电设备的无线电设备和无线电传输/接收系统
公开(公告)号：JP2006108755A
公开(公告)日：2006-04-20
申请号：JP2004288473
申请日：2004-09-30
申请人： Nippon Precision Circuits Inc , 日本プレシジョン・サーキッツ株式会社
发明人： KAYAMA SATOSHI
IPC分类号： H04B1/59 , G06K17/00 , G06K19/07 , G08C17/00 , H04B5/02
CPC分类号： Y02D70/00 , Y02D70/10 , Y02D70/40 , Y02D70/42
摘要： PROBLEM TO BE SOLVED: To provide radio equipment such as a wireless tag capable of attaining the long lifetime of a power supply battery by saving power of the radio equipment in its operation. SOLUTION: Each of the wireless tags T1 to Tn includes: a transmission section 1; a reception section 2; a timer 3; a memory 4; a microcomputer 5; the power supply battery 6; an A/D converter 7; and a sensor 8, the memory 4 stores a preset ID, a response (transmission) ranking set in advance similarly to above, and reference data with which detected data sensed by the sensor 8 and digitized by the A/D converter 7 are compared, the timer 3 sets a transmission start time, and each of the wireless tags includes a mode wherein all IDs alternatively selected are transmitted in the ID transmission and a mode wherein parts of the IDs are transmitted, and includes a mode wherein all of the detected data alternatively selected are transmitted and a mode wherein only the data resulting from comparison arithmetic operations between the detected data and the reference data by the microcomputer are transmitted in the transmission of the detected data. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过节省无线电设备在其操作中的功率，提供能够实现电源电池的长寿命的无线电标签的无线电设备。解决方案：每个无线标签T1至Tn包括：传输部分1; 接收部分2; 定时器3; 存储器4; 微型计算机5; 电源电池6; A / D转换器7; 和传感器8，存储器4存储预先设定的ID，与上述相同的预先设定的响应（发送）等级，并且比较由传感器8感测并被A / D转换器7数字化的检测数据的参考数据，定时器3设定发送开始时间，并且每个无线标签包括其中在ID发送中发送所有选择的所有ID的模式以及发送部分ID的模式，并且包括其中所有检测到的数据发送可选择的方式以及在检测数据的发送中仅发送由微型计算机检测到的数据与参考数据之间的比较算术运算产生的数据的模式。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2006087059A Apparatus and method for generating equaly spaced pulse train 有权
标题翻译：用于产生均匀脉冲脉冲串的装置和方法
公开(公告)号：JP2006087059A
公开(公告)日：2006-03-30
申请号：JP2004299382
申请日：2004-09-14
申请人： Nippon Precision Circuits Inc , 日本プレシジョン・サーキッツ株式会社
发明人： KANEHACHI KAORU , TOYAMA AKIRA
IPC分类号： H03K5/1536 , G06F1/04 , H03K5/26
摘要： PROBLEM TO BE SOLVED: To provide a phase composition apparatus and a phase composition method in which a power consumption is reduced and an accurate output wave without causing any variation of a frequency can be obtained. SOLUTION: The phase composition apparatus has a linear interpolation circuit, which is provided with: a D/A converter 2 for sampling/holding a differential between phase data synchronized with a clock and phase data before and after a cross point with a predetermined voltage value and then converting the differential into an analog value; an integrator 5 comprised of a current source 3 for converting the analog value converted by the D/A converter into a current and a capacitor 4 for temporally integrating said current; and a reset circuit 6 for discharging electric charges of the integrator. In this method, an accurate output wave of reduced jitter can be composited without being affected by a gain change of the capacitor or a DC offset error in D/A conversion by using the phase composition apparatus. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种相位合成装置和相位组合方法，其中功耗降低，并且可以获得精确的输出波，而不会导致频率的任何变化。相位合成装置具有线性插补电路，该线性插值电路具有：D / A转换器2，用于采样/保持与时钟同步的相位数据之间的差分，以及在交叉点之前和之后的相位数据然后将该差分变换为模拟值; 由电流源3构成的积分器5，用于将由D / A转换器转换的模拟值转换为电流;电容器4，用于对所述电流进行时间积分; 以及用于对积分器的电荷进行放电的复位电路6。在该方法中，通过使用相位合成装置，可以在不受电容器的增益变化或D / A转换中的DC偏移误差的影响的情况下合成精确的抖动抖动输出波。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2005318122A Charge pump circuit and pll circuit using the same 有权
标题翻译：充电泵电路和使用相同的PLL电路
公开(公告)号：JP2005318122A
公开(公告)日：2005-11-10
申请号：JP2004132017
申请日：2004-04-27
申请人： Nippon Precision Circuits Inc , 日本プレシジョン・サーキッツ株式会社
发明人： KAWAI HIROSHI , OTSUKA HARUHIKO
IPC分类号： H03K17/06 , H03K19/0175 , H03L7/089 , H03L7/093 , H03L7/095 , H03L7/107 , H03L7/18
CPC分类号： H03L7/0893 , H03L7/0896 , H03L7/095 , H03L7/107 , H03L7/18
摘要： PROBLEM TO BE SOLVED: To improve the jitter characteristics and spectral characteristics of a PLL circuit, by reducing the operating noise and charge errors of a charge pump circuit, and further, to shorten the time, until the PLL circuit is locked. SOLUTION: A control signal generated by a control circuit 5 generates the control signal, corresponding to the output of a phase comparison/lock detecting circuit 4 and is inputted to the charge pump circuit 6. The charge pump circuit 6 is provided with four current sources 61, 62, 63, and 64, three P-channel MOS transistors P1, P2, and P3, and three N-channel transistors N1, N2, and N3. The transistor P1 is turned on/off by the up-signal of the phase comparison/lock detecting circuit 4. The transistor N1 is turned on/off by the down-signal of the phase comparison/lock detecting circuit 4. Each of the transistors P2, P3, N2, and N3 is turned on/off, on the basis of the control signal of the control circuit 5. Consequently, the output signal from a VCO control terminal 65 is inputted to a VCO8 via a low-pass filter 7, while a current is made to always flow to the charge pump circuit 6. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过降低电荷泵电路的工作噪声和充电误差来提高PLL电路的抖动特性和频谱特性，并且缩短时间，直到PLL电路被锁定为止。解决方案：由控制电路5产生的控制信号产生对应于相位比较/锁定检测电路4的输出的控制信号，并输入到电荷泵电路6.电荷泵电路6设有四个电流源61,62,63和64,3个P沟道MOS晶体管P1，P2和P3以及三个N沟道晶体管N1，N2和N3。晶体管P1由相位比较/锁定检测电路4的上升信号导通/截止。晶体管N1通过相位比较/锁定检测电路4的下降信号导通/截止。每个晶体管基于控制电路5的控制信号，P2，P3，N2和N3导通/截止。因此，来自VCO控制端65的输出信号通过低通滤波器7被输入到VCO8 ，而电流总是流向电荷泵电路6.版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2005236536A Distributed modulation clock generating circuit 有权
标题翻译：分布式调制时钟发生电路
公开(公告)号：JP2005236536A
公开(公告)日：2005-09-02
申请号：JP2004041532
申请日：2004-02-18
申请人： Nippon Precision Circuits Inc , 日本プレシジョン・サーキッツ株式会社
发明人： HATTORI YUJI
IPC分类号： H03K7/08 , H03L7/183 , H03L7/197
CPC分类号： H03L7/197
摘要： PROBLEM TO BE SOLVED: To provide a distributed modulation clock generating circuit in which EMI with peripheral apparatus is reduced. SOLUTION: The distributed modulation clock generating circuit comprises a PLL system 1, and a clock modulation circuit 11 provided with a ΔΣ modulator 15. Frequency of an output clock is modulated by modulating the frequency division number of a frequency divider 8 in a PLL system 1 through a digital circuit. Furthermore, a modulation pattern controller 13 varies the amplitude and period by distributing the changing points where a triangular wave, i.e. a modulation waveform being generated from a modulation pattern generator 12, rises or falls. Consequently, the problem of distortion in an analog circuit is eliminated and an output clock exhibiting a better modulation efficiency as compared with an ordinary case using a triangular wave is attained. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种分布式调制时钟发生电路，其中与外围设备的EMI减少。解决方案：分布式调制时钟发生电路包括PLL系统1和设置有ΔΣ调制器15的时钟调制电路11.通过调制分频器8的分频数来调制输出时钟的频率 PLL系统1通过数字电路。此外，调制图案控制器13通过分配三角波（即，从调制图案生成器12生成的调制波形）上升或下降的变化点来改变振幅和周期。因此，与使用三角波的普通情况相比，消除了模拟电路的失真问题，并且具有更好的调制效率的输出时钟。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2005235836A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2005235836A
公开(公告)日：2005-09-02
申请号：JP2004039755
申请日：2004-02-17
申请人： Nippon Precision Circuits Inc , 日本プレシジョン・サーキッツ株式会社
发明人： KAMIJO MAKOTO , TAKAHASHI KATSUYUKI
IPC分类号： G11C17/08 , H01L27/10
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device wherein insulation breakdown can be caused in an insulation film by the application of a writing voltage not higher than a source/drain breakdown voltage, and which is used as an antifuse which is guaranteed for an initial insulation property before writing. SOLUTION: The semiconductor memory device used as an antifuse includes a MOS capacitor 4 which comprises a semiconductor substrate 1, a well 2 formed on the semiconductor substrate 1, a diffusion layer 41 existing inside the well 2, and an insulation film 42 and 43 and a conductor film 44 which are deposited in order on the diffusion layer 41. The insulation film 42 and 43 of the MOS capacitor 4 has such a structure that the insulation film 43 at the center is formed thinner than the insulation film 42 in the periphery. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种半导体存储器件，其中通过施加不高于源极/漏极击穿电压的写入电压，可以在绝缘膜中引起绝缘击穿，并且其用作反熔丝，其为保证写入前的初始绝缘性能。解决方案：用作反熔丝的半导体存储器件包括MOS电容器4，其包括半导体衬底1，形成在半导体衬底1上的阱2，存在于阱2内部的扩散层41和绝缘膜42 43和导体膜44依次沉积在扩散层41上.MOS电容器4的绝缘膜42和43具有这样的结构，使得中心的绝缘膜43形成为比绝缘膜42更薄周边。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2005210266A Receiving circuit and time correction apparatus employing the same 审中-公开
标题翻译：接收电路和使用其的时间校正装置
公开(公告)号：JP2005210266A
公开(公告)日：2005-08-04
申请号：JP2004012777
申请日：2004-01-21
申请人： Nippon Precision Circuits Inc , Seiko Clock Inc , セイコークロック株式会社 , 日本プレシジョン・サーキッツ株式会社
发明人： NAKAMURA HIDEYUKI , TAKAHASHI MASAYUKI
IPC分类号： G04G5/00 , G04R20/00 , G04R20/10 , H03G3/20 , H03G3/30 , H04B1/16 , G04C9/02
摘要： PROBLEM TO BE SOLVED: To prevent erroneous discrimination of a receiving state when a plurality of frequencies are received and reduce time until an input signal is stabilized after a receiving frequency is switched. SOLUTION: A receiving circuit applies feedback control to a GCA2 in order to maintain the detection output with respect to a radio wave received by an antenna 1 to a first potential and switches the level of a capacitor 5 to a first standby level. When the receiving circuit selectively receives a plurality of radio waves whose reception frequencies differ from each other and receives a radio wave in a superior state after comparing the reception results, the receiving circuit can start the reception of the radio waves of the succeeding frequency without being affected by the receiving state of the radio waves of the previous frequency. Thus, it is possible to set the condition of the receiving circuit identically when receiving the radio waves of various frequencies and the receiving state can accurately be compared and discriminated. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了防止接收多个频率时的接收状态的错误判别，并且在接收频率切换之后直到输入信号稳定为止。解决方案：接收电路向GCA2施加反馈控制，以便将相对于由天线1接收到的无线电波的检测输出保持为第一电位，并将电容器5的电平切换到第一备用电平。当接收电路选择性地接收多个接收频率彼此不同的无线电波并且在比较接收结果之后接收上位状态的无线电波时，接收电路可以开始接收后续频率的无线电波，而不会受前一频率的无线电波的接收状态的影响。因此，可以在接收各种频率的无线电波时设置接收电路的状态，并且可以准确地比较和判别接收状态。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2005151045A Latched comparator 有权
标题翻译：锁定比较器
公开(公告)号：JP2005151045A
公开(公告)日：2005-06-09
申请号：JP2003384057
申请日：2003-11-13
申请人： Nippon Precision Circuits Inc , 日本プレシジョン・サーキッツ株式会社
发明人： HASEGAWA EIICHI , NOINE SHUNSUKE
IPC分类号： H03K5/08
摘要： PROBLEM TO BE SOLVED: To provide a latched comparator in which output converges quickly even if a signal voltage is equal to a reference one.
SOLUTION: The latched comparator has a voltage comparison circuit 110 for comparing the signal voltage with the reference one for outputting the comparison result, and a latching circuit 150 for retaining the comparison result outputted from the voltage comparison circuit by the control of a clock signal. In the comparator, the latching circuit 150 has an equal threshold voltage, and at least three stages of inverters 130, 131, 132 that are connected in cascade. In the second stage or thereafter in the inverter, the output terminal is connected to the input terminal of the inverter at a stage prior by one, and voltage outputted from the voltage comparison circuit 110 when the signal voltage is equal to the reference one is equal to the threshold voltage of the inverter.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种锁存比较器，其中即使信号电压等于参考电压，其输出也快速收敛。解锁：锁存比较器具有电压比较电路110，用于将信号电压与参考电压进行比较，以输出比较结果;以及锁存电路150，用于通过控制电压比较电路来保持从电压比较电路输出的比较结果时钟信号。在比较器中，锁存电路150具有相等的阈值电压，以及级联连接的至少三级的反相器130,131,132。在第二级或其后的逆变器中，输出端子在一级之前的一级连接到逆变器的输入端子，当信号电压等于参考值时，从电压比较电路110输出的电压相等到逆变器的阈值电压。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2005150978A Apparatus of amplifying minute detection signal of sensor 审中-公开
标题翻译：放大检测信号传感器的设备
公开(公告)号：JP2005150978A
公开(公告)日：2005-06-09
申请号：JP2003383070
申请日：2003-11-12
申请人： Nippon Precision Circuits Inc , 日本プレシジョン・サーキッツ株式会社
发明人： TEI HIROSUKE , KASAI HIROYUKI , YANO KAZUYA
IPC分类号： G01D3/02 , G01J1/42 , G01J1/44 , H03F3/34
摘要： PROBLEM TO BE SOLVED: To provide an apparatus of amplifying a minute detection signal of a sensor which is capable of performing high-precision offset canceling and reducing noise in a low-frequency region.
SOLUTION: A first switching element 11 is provided for allowing the input terminal 2a of an operational amplifier 2 for inputting an output signal of a sensor 1 to selectively conduct with an output terminal 1a of the sensor 1 or with a reference potential 40. One terminal 31a of a capacitor 31 is connected to an output terminal 2c of the operational amplifier 2, and the other terminal 31b is connected to an output buffer 3. A second switching element 12 is provided for allowing the terminal 31b to selectively conduct with the reference potential 40, and the capacitor 31 is charged with an offset voltage in a state where each of switching elements 11, 12 is allowed to conduct with the reference potential 40. Subsequently, the element 12 is brought into a non-conduction status with the reference potential 40 and is held in this status. Then the element 11 is brought into a conduction status with the output terminal 1a of the sensor 1, the offset voltage is canceled, and the noise in a low-frequency region is reduced.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种放大能够执行高精度偏移消除并降低低频区域噪声的传感器的微小检测信号的装置。解决方案：提供第一开关元件11，用于允许用于输入传感器1的输出信号的运算放大器2的输入端子2a选择性地与传感器1的输出端子1a或参考电位40 电容器31的一个端子31a连接到运算放大器2的输出端子2c，另一个端子31b连接到输出缓冲器3.第二开关元件12用于允许端子31b选择性地与参考电位40和电容器31在允许开关元件11,12中的每一个与参考电位40导通的状态下被充电偏移电压。随后，元件12进入非导通状态参考电位40并保持在该状态。然后元件11与传感器1的输出端1a进入导通状态，偏移电压被消除，低频区域的噪声降低。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JP3646236B2 Crystal oscillator circuit and crystal oscillator for an integrated circuit device 失效
公开(公告)号：JP3646236B2
公开(公告)日：2005-05-11
申请号：JP576597
申请日：1997-01-16
申请人：日本プレシジョン・サーキッツ株式会社
发明人：大塚晴彦 , 長谷川栄一
IPC分类号： H03B5/32 , H03B5/36 , H03K3/012 , H03K3/03
CPC分类号： H03K3/0307 , H03B5/36 , H03K3/012

10. 发明专利

JP3632111B2 Semiconductor device 失效
公开(公告)号：JP3632111B2
公开(公告)日：2005-03-23
申请号：JP14637095
申请日：1995-06-13
申请人：日本プレシジョン・サーキッツ株式会社
发明人：清野達也
IPC分类号： H01L21/301

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