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1. 发明专利

JPS56107789A VARIABLE MAGNETIC PERMEABILITY TYPE MAGNETIC DRIVE SYSTEM 失效
公开(公告)号：JPS56107789A
公开(公告)日：1981-08-26
申请号：JP826280
申请日：1980-01-29
申请人： KATAYAMA AISUKE
发明人： KATAYAMA AISUKE
IPC分类号： H02N2/00 , H02K53/00
摘要： PURPOSE:To generate stable and continous and high drive force by a magnetic unit by generating magnetic energy by means of the variation in the magnetic permeability of the magnetic unit. CONSTITUTION:A variable magnetic unit 2 formed of fluid ferrite or the like is arranged in a gap between stationary magnetic units 1. Further, a magnetic property varying unit 3 is provided at the right side of the magnetic unit 1. When the movable magnetic unit 2 of the fluid ferrite is located in the gap of the magnetic unit 1, the magnetic permeability of the magnetic unit 2 is retained at relatively high value. When the magentic unit 2 moves rightwardly in the gap, the magnetic permeability of the magnetic unit 2 is reduced by the magnetic property varying unit 3. Thus, since the magnetic energy of the magnetic unit 2 is increased, force for reducing the magnetic energy is operated to draw the magnetic unit 2 in the gap of the magnetic unit 1.

2. 发明专利

JPH04348422A DIVIDED PRODUCT TYPE MULTIPLIER 失效
公开(公告)号：JPH04348422A
公开(公告)日：1992-12-03
申请号：JP17271191
申请日：1991-07-12
申请人： KATAYAMA AISUKE , NEC CORP
发明人： KATAYAMA AISUKE
IPC分类号： G06F7/52 , G06F7/523 , G06F7/525 , G06F7/533
摘要： PURPOSE:To perform the multiplication of high digit numerical values with high accuracy. CONSTITUTION:A multiplier multiplies a multiplicand X by a multiplier Y and outputs a product Q of the X and the Y. Then a multiplying circuit 14 of the multiplier multiplies i (0 >i] of the X by j (0 >j] and outputs a divided product p (x>>i], y>>j]). This product p (x>>i], y>>j]) is calculated by changing successively a rank number (k)(k=i+j). An accumulation circuit 18 selects the divided products having one rank number in common based on the rank number (k) in order to successively accumulate the divided product (p). Then the circuit 18 outputs successively and ascendingly the products Q up to the (N+M-1) digit q>>N+M-1] from the O digit q>>o]. A reading circuit 13 refers to the number (k) to successively read the (i) digit x>>i] of the X and the j digit y>>j] out of an i-th multiplicand address of a multiplicand memory 11 and a j-th multiplier address of a multiplier memory 12 respectively.

3. 发明专利

JPS54144148A EXPONENTIAL CONVERSION TYPE HIGH SPEED MULTIPLYING SYSTEM 失效
公开(公告)号：JPS54144148A
公开(公告)日：1979-11-10
申请号：JP5074778
申请日：1978-05-01
申请人： KATAYAMA AISUKE
发明人： KATAYAMA AISUKE , ITOU JIYUNICHI
IPC分类号： G06F7/53 , G06F1/03 , G06F7/508 , G06F7/72

4. 发明专利

JP2001051828A METHOD AND DEVICE FOR PAIR-DOWN MULTIPLICATION AND COMPUTER-READABLE RECORDING MEDIUM 失效
公开(公告)号：JP2001051828A
公开(公告)日：2001-02-23
申请号：JP2000163140
申请日：2000-05-29
申请人： NEC CORP , KATAYAMA AISUKE
发明人： KATAYAMA AISUKE
IPC分类号： G06F7/53 , G06F7/52 , G06F7/527
摘要： PROBLEM TO BE SOLVED: To perform fast and errorless multiplication of a large number of digits, needed for operation of very large numbers in a field of space science, etc. SOLUTION: Of a multiplication device which finds the product Q of a multiplicand X having N digits (N>=2) in L-ary notation (L>=2) and a multiplier Y with M digits (M>=2) in L-ary notation, a partial product calculating means 12 calculates partial products with N+1 digits as the product of each of the numerals of the digits of the multiplier Y and the multiplicand X and stores them in a work memory 16 in the form of an array. A pair-down arithmetic means 13 pairs adjacent partial products calculated by the calculating means 12 in order from the partial product corresponding to the numeral of the 0th digit of the multiplier Y to the partial product corresponding to the numeral of the (M-1)th digit to sequentially derive the numerals of the respective digits constituting the product Q through an oblique adding process and a carry process.

5. 发明专利

JPH05204610A MULTIPLIER WITH TAIL DIGIT ARRAY 失效
公开(公告)号：JPH05204610A
公开(公告)日：1993-08-13
申请号：JP247192
申请日：1992-01-09
申请人： NEC CORP , KATAYAMA AISUKE
发明人： KATAYAMA AISUKE
IPC分类号： G06F7/496 , G06F7/52 , G06F7/523
摘要： PURPOSE:To speed up multiplication by dividedly executing carry processing and the direct output of a tail digit array during the processing of a digit product and obtaining a final product. CONSTITUTION:A multiplicand X consisting of N digits (N>=2), i.e., the 0th digit (x[0]) to (N-1)th digit (x[N-1]) expressed by L-digit-advance numbers (L>=2) is multiplied by a multiplier Y consisting of M (M>=2) digits, i.e., the 0th digit (y[0]) to (M-1)th digit (y[M-1]) expressed by L-digit-advance numbers (L>=2) to find out the product Q of the X and Y. In this case, the array product of an X array x[i]0 i N-1 and a Y array y[j] 0 j N-1 is defined as x[i]*y[j]= P[i][j], the order (k) of the value (i+j) is defined and P[i, j] is formed in the ascending order of (k) based upon equations I to III. Then tail digit array are successively calculated without using accumulation by attaining execution in the digit order of digit products by the repeat of unit operation based upon the output of a tail digit array, the carry of a residual number and addition to the succeeding digit product.

6. 发明专利

JPS5760661B2 失效
公开(公告)号：JPS5760661B2
公开(公告)日：1982-12-21
申请号：JP5074778
申请日：1978-05-01
申请人： KATAYAMA AISUKE
发明人： KATAYAMA AISUKE , ITO JUNICHI
IPC分类号： G06F7/53 , G06F1/03 , G06F7/508 , G06F7/72

7. 发明专利

JPS5839286A BELTLIKE FIN TYPE RING MAGNETIC SUBSTANCE AND GENERATING SET USING SAID SUBSTANCE 失效
公开(公告)号：JPS5839286A
公开(公告)日：1983-03-07
申请号：JP13705481
申请日：1981-09-02
申请人： KATAYAMA AISUKE
发明人： KATAYAMA AISUKE
IPC分类号： H02N10/00
摘要： PURPOSE:To change heat applying power into mechanically continuous power with high efficiency by circulating an annular magnetic substance, in the direction of rotation thereof a large number of projecting sections are formed, to a heating section to which a magnetic pole is juxtaposed and a cooling section at fixed speed. CONSTITUTION:A heating section 2 and a magnetic-field applying section 3 are fixed at an pproximately stacked position. A ring-shaped magnetic substance 1 circulates the heating section 2 and the magnetic-field applying section 3, passes through the heating section as well as the magnetic-field applying section, and enters a cooling section 4. Accordingly, the magnetic-substance ring 1 repeats the cycle of heating, the application of a magnetic field and cooling at the predetermined speed of revolution. Output torque power generated in the magnetic-substance ring 1 is converted into electric power by means of a generator 6 and taken out for use.

8. 发明专利

JPS55162148A MULTIPLE RULE TYPE HIGH SPEED MULTIPLICATION SYSTEM 失效
公开(公告)号：JPS55162148A
公开(公告)日：1980-12-17
申请号：JP6749579
申请日：1979-06-01
申请人： KATAYAMA AISUKE
发明人： KATAYAMA AISUKE
IPC分类号： G06F7/53 , G06F7/493 , G06F7/508 , G06F7/52 , G06F7/523 , G06F7/72
摘要： PURPOSE:To obtain the product remainder of a true product by composing the system of two exponent index transformation ROMs, receiving multiplicands X and multipliers Y as addresses, one inverse exponent transformation ROM and a h-digit adder. CONSTITUTION:Multiplicand X and multiplier Y are h-digit binary numerals, which are divided into high-order and low-order digit bits XH and XL, and YH and YL. Then, ROM1 stores the product of new low-order digit split numerals XL and YL and the digits consists of 2 Xh bits. Next, ROMs 2 and 3, of the same constitution, store only low-order bits of the product of high-order and low-order bits of an address input and when the address input of XHYL and XLYH is done, low-order P1L and P2L of the products of high-order and low-order bits are output. To the terminal of h/2-bit adder 4, XLYL=P3H.P3L is applied and the sum bit is applied to the next h/2-bit adder 5 together with output P2L of ROM3 to obtain product remainder rp2 in the 2 modulus as the sum bit. The time of finding the product remainder is the sum of the time of access to ROMs, but since there is no need to consider a carry when the number of digits is small, the addition time can be ignored and high speed multiplication comes into effect.

9. 发明专利

JPH10228369A HIGH SPEED MULTIPLICATION DEVICE AND HIGHLY ACCURATE HIGH DIGIT MULTIPLICATION DEVICE 失效
公开(公告)号：JPH10228369A
公开(公告)日：1998-08-25
申请号：JP3347297
申请日：1997-02-18
申请人： NEC CORP , KATAYAMA AISUKE
发明人： KATAYAMA AISUKE
IPC分类号： G06F7/53 , G06F7/496 , G06F7/506 , G06F7/52 , G06F7/525
摘要： PROBLEM TO BE SOLVED: To provide a highly accurate high digit multiplication device capable of highly accurately executing the multiplication of high digits by using only an aritmetic means of one digit. SOLUTION: An one-digit partial product arithmetic circuit 14 receives the (n+1)th digit element x [n] of a multiplier X and the (m+1) th digit element y [m] of a multiplier Y respectively from a multiplicand memory 11 and a multiplier memory 12 and successively finds out an one-digit partial product u [m, k] by using only an one-digit arithmetic means not including an arithmetic means of two digits or more. An one-digit product arithmetic means 18 receives the one-digit partial product u [m, k] and successively finds out the (d+1) th digit element q [d] of a product Q in ascending order from the 1st digit element q [O] up to the D-th digit element q [D-1] by using an one-digit arithmetic means not including an arithmetic means of two digits or more.

10. 发明专利

JPH06242929A HIGH-SPEED REMAINDER ARRAY TYPE DIVISION SYSTEM 失效
公开(公告)号：JPH06242929A
公开(公告)日：1994-09-02
申请号：JP2462393
申请日：1993-02-15
申请人： NEC CORP , KATAYAMA AISUKE
发明人： KATAYAMA AISUKE
IPC分类号： G06F7/496 , G06F7/493 , G06F7/52
摘要： PURPOSE:To perform high-speed and highly precise division by using a computer. CONSTITUTION:A dividend is first decomposed into the array X[i] X[i-1]...X[1], X[0] of the integers of M digits or M+1 digits from a highest digit and the integers of each succeeding digit. A processing for obtaining the quotient of (i)-th digit and the remainder by dividing X[i]by a divisor and then obtaining the quotient of (i-1)-th digit and the remainder by dividing a number whose higher digit is the remainder and lower digit is X[i-1] by the divisor is repeated and the quotient and the remainder are finally obtained.

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