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1. 发明专利

JP2012109403A SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREFOR 审中-公开
公开(公告)号：JP2012109403A
公开(公告)日：2012-06-07
申请号：JP2010257161
申请日：2010-11-17
申请人： ELPIDA MEMORY INC , HITACHI ULSI SYS CO LTD
发明人： KUBONAI SHUICHI , NAKAJIMA DAIKI
IPC分类号： H01L21/82 , G11C29/00 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a plurality of electric fuses in various conduction states in which the results programmed by the plurality of electric fuses can be read without being determined erroneously, and to provide a control method therefor.SOLUTION: The semiconductor device comprises a plurality of fuse elements which are in a program state or a non-program state, respectively, a plurality of fuse determination circuits 92a, 92b which output determination result signals FLDa, FLDb corresponding to the program state or non-program state of the plurality of fuse elements, respectively, and a plurality of latch circuits 93a, 93b which receive a first timing signal LOAD_END commonly, and latch and output a plurality of determination result signals FLDa, FLDb in synchronism with the first timing signal LOAD_END.

2. 发明专利

JP2006351173A SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS 审中-公开
公开(公告)号：JP2006351173A
公开(公告)日：2006-12-28
申请号：JP2006164272
申请日：2006-06-14
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： TANAKA HITOSHI , AOKI MASAKAZU , KIMURA SHINICHIRO , NODA HIROMASA , SEKIGUCHI TOMONORI
IPC分类号： G11C11/407 , G06F1/26 , G11C11/408 , H01L21/822 , H01L21/8238 , H01L21/8242 , H01L27/04 , H01L27/092 , H01L27/10 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit apparatus equipped with a stably operated internal power supply circuit or the like. SOLUTION: This apparatus is provided with a power supply circuit operated by a power supply voltage from the outside to form an internal voltage, and an internal circuit to which the internal voltage is applied. A variable impedance means is provided between the output voltage of a charge pump circuit and the internal voltage. A differential amplifying circuit controls the variable impedance means so that a reference voltage corresponding to the internal voltage is compared with the internal voltage and the both are coincident with each other. A power supply circuit is constituted of a first power supply circuit for forming a voltage having a polarity same as that of the voltage supplied from the outside and a second power supply circuit for forming a voltage having a polarity different from the voltage supplied from the out side. The output voltage of the charge pump circuit of the first power supply circuit is applied to an N-well having a P-well forming elements constituting an internal circuit formed therein. The output voltage generated by the charge pump circuit of the second power supply circuit is used also as a substrate back-bias voltage applied to the P-well having the elements constituting the internal circuit formed therein. COPYRIGHT: (C)2007,JPO&INPIT

3. 发明专利

JP2004006479A SEMICONDUCTOR STORAGE DEVICE 审中-公开
公开(公告)号：JP2004006479A
公开(公告)日：2004-01-08
申请号：JP2002159258
申请日：2002-05-31
申请人： ELPIDA MEMORY INC , HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： FUJISAWA HIROKI , ARAI KOJI , DONO CHIAKI
IPC分类号： G11C11/401 , G11C5/02 , G11C8/02 , G11C8/14 , G11C11/408 , G11C11/4097 , H01L21/8242 , H01L27/02 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device having multilayer wiring structure wherein restriction of a conventional multilayer wiring structure of main wordlines and YS lines is pointed out, and limit concerning the number of wiring lines due to the restriction can be eliminated. SOLUTION: In the semiconductor storage device having the multilayer wiring structure wherein series selecting lines (YS) extended in a Y direction and main wordlines (MWL) extended in an X direction are subjected to multilayer wiring, the semiconductor storage device having structure wherein a wiring layer of the YS is arranged lower than a wiring layer of the MWL can be obtained. By this structure, in a subword driver (SWD) region which is arranged intersecting the X direction, the MWL wiring is arranged on the uppermost layer, a subword selecting line (FXT/B) wiring layer is formed in a lower layer of the MWL wiring, and the number of island patterns in the lower layer wiring layer can be reduced. As the result, a plurality of power source lines, etc. can be arranged in a space between adjacent MWLs in the SWD region. COPYRIGHT: (C)2004,JPO

4. 发明专利

JP2003258022A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 审中-公开
公开(公告)号：JP2003258022A
公开(公告)日：2003-09-12
申请号：JP2002061765
申请日：2002-03-07
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： NAKAJIMA YASUYUKI , MORITA TOSHIAKI , MATSUZAWA ASAO , TOMOI HARUICHI , KAWABE NAOKI
IPC分类号： H01L21/60 , H01L23/485 , H01L23/532
摘要： PROBLEM TO BE SOLVED: To improve the reliability of a semiconductor device by improving adhesion between a bonding pad of wiring and a ball of a bonding wire. SOLUTION: When the ball B of the bonding wire is adhered on the bonding pad BP wherein an Al film M3b is exposed on third layer wiring composed of a TiN film, an Al film M3b and a TiN film on a semiconductor substrate, the relation between a connection region d between the Al film 3b and a gold ball B, and the diameter g of the formation region of an Al-Au alloy layer 50 between the Al film M3b and the gold ball B is made g≥0.8 d; and the relation between the diameter d of a contact region and the maximum outer circumferential diameter D of the gold ball B is made d≥0.8 D. As a result, even if the Al film M3b (the third layer wiring) is a thin film, adhesion to the gold ball B can be secured and a short margin can be secured. COPYRIGHT: (C)2003,JPO

5. 发明专利

JP2003257197A SEMICONDUCTOR MEMORY CIRCUIT, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003257197A
公开(公告)日：2003-09-12
申请号：JP2002054359
申请日：2002-02-28
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD , ELPIDA MEMORY INC
发明人： OSAKABE TOSHIAKI
IPC分类号： G06F12/16 , G06K19/07 , G06K19/077 , G11C29/00 , G11C29/04
摘要： PROBLEM TO BE SOLVED: To operate either of memory chips which is interchangeable between a semiconductor device including two memory chips having the same specifications and a semiconductor device including one memory chip having the said specifications. SOLUTION: In the case that newly provided input/output pin group selecting switch circuit SW3, SW4 in addition to existent circuits on an upper chip and a lower chip are desirably controlled from an option pad OPPAD2 being in a desired potential through a fuse F2 being in a cut-off/uncut-off state, also, operation power source supply ayes and noes selecting switch circuits SW1, SW2 are desirably controlled from option pads OPPAD1, OPPAD3 being in a desired potential through fuses F1, F3 being in cut-off/uncut-off state, either of chips can be interchangeable between a semiconductor device including two memory chips and a semiconductor device including one chip having the same specifications. COPYRIGHT: (C)2003,JPO

6. 发明专利

JP2003256354A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
公开(公告)号：JP2003256354A
公开(公告)日：2003-09-12
申请号：JP2002053004
申请日：2002-02-28
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： SUZUKI TAKAAKI , UEHARA MOTOKI , IKEDA TAKENOBU
IPC分类号： G06F13/28 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of improving data transmitting efficiency in a simple structure and including DMAC being easy to handle in a simple structure. SOLUTION: In the DMAC having a plurality of channels, the DMAC provides a first register that makes the channels and an interface circuit corresponding to the channels coped together, and a second register having the same structure with the first register. Setting of a channel can be performed on the first and second registers in a first mode, setting of a channel can be also performed on the first register only in a second mode, and transmission of setting information data for the channel already set on the second register is performed. COPYRIGHT: (C)2003,JPO

7. 发明专利

JP2003243313A VERTICAL CVD SYSTEM AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING IT 审中-公开
公开(公告)号：JP2003243313A
公开(公告)日：2003-08-29
申请号：JP2002041133
申请日：2002-02-19
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KURODA ATSUSHI , ANDO TOSHIO
IPC分类号： C23C16/44 , H01L21/205 , H01L21/22 , H01L21/31
摘要： PROBLEM TO BE SOLVED: To improve throughput of a vertical CVD system and, in addition, to shorten developing or producing period of a product. SOLUTION: In the vertical CVD system, a semiconductor wafer sorter chamber is provided under a reaction chamber which is heated from the outside by means of a heating means for heat treatment, and a semiconductor wafer boat is provided in the sorter chamber in an automatically vertically movable state. In the periphery of the semiconductor wafer boat, a heating means is provided for preheating semiconductor wafers before heat treatment. COPYRIGHT: (C)2003,JPO

8. 发明专利

JP2003203969A METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003203969A
公开(公告)日：2003-07-18
申请号：JP2002001899
申请日：2002-01-09
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： OTA HIROSHI , HIRATA KOJI , KIKAWA TAKESHI
IPC分类号： H01L21/331 , H01L21/338 , H01L21/76 , H01L29/737 , H01L29/778 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To solve the problem in the case of isolation of semiconductor elements, such as deterioration of characteristics due to deterioration in crystallinity, increase of leakage current due to contact of an active layer with electrode metal, and step cut of the electrode metal and wiring metal in a step difference part. SOLUTION: In a method for forming an active layer in an element part of a semiconductor wafer by using an ion implanting method or a diffusion method, or an element isolation method of a semiconductor element, by increasing electrical resistance of a part except an element part after the active layer is formed over the whole semiconductor wafer, this method for manufacturing a semiconductor device includes a process for forming the active layer on a semiconductor substrate, a process for forming a spacer layer for lift-off on an upper layer of the active layer, a process for anisotropically working the spacer layer, a process for working a semiconductor layer containing the active layer, by using the spacer layer or mask material for working the spacer layer as a mask, a process for directivity-depositing an insulating film on the spacer layer and on the entire surface of an exposed semiconductor layer, and a process for eliminating the spacer layer, by using an etching agent for etching and eliminating only the spacer layer. COPYRIGHT: (C)2003,JPO

9. 发明专利

JP2003195956A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
公开(公告)号：JP2003195956A
公开(公告)日：2003-07-11
申请号：JP2001391235
申请日：2001-12-25
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： SAITO YOSHIKAZU
IPC分类号： G11C11/413 , G05F1/56 , G05F1/565 , G11C5/14 , H01L21/822 , H01L27/04 , H03F1/30 , H03F3/45 , H03K19/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having a negative feedback amplifying circuit or a voltage drop circuit for stabilizing output voltage by effectively responding to a fluctuation in source voltage. SOLUTION: A bias current for setting a consuming electric current is made to flow to a differential amplifying MOSFET by a constant current source. A capacitor is arranged between external source voltage and a prescribed circuit node. A drop in the external source voltage is detected by the capacitor. An operating current of the amplifying MOSFET is increased by using an electric current flowing to the capacitor by such an external power source fluctuation to perform stabilizing operation of the output voltage corresponding to the drop in the external source voltage. COPYRIGHT: (C)2003,JPO

10. 发明专利

JP2003179103A SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR 审中-公开
公开(公告)号：JP2003179103A
公开(公告)日：2003-06-27
申请号：JP2001379938
申请日：2001-12-13
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： TOJO SHINJI , ICHIHARA SEIICHI , KANEMITSU NOBUYA
IPC分类号： H01L21/60
摘要： PROBLEM TO BE SOLVED: To improve the bending slit part of a lead of a semiconductor device in bending strength and to restrain a tin plating layer from affecting the manufacturing of a semiconductor device, even if the tin plating layer formed on a lead becomes defective. SOLUTION: In a semiconductor device, a tin plating layer is formed on the copper lead of a tape carrier package; a copper foil 2 is provided on an insulating tape 1 and formed into a lead 3 through etching; and a first solder resist layer 9 is applied on the bent part of the lead 3, a first tin-plating operation is performed on the lead 3 in this state, a second solder resist layer is applied on a part of the lead 3 other than an outer lead and an inner lead which are plated with tin once, the outer lead and the inner lead once plated with tin are plated with tin once again, the inner lead and the electrode of a semiconductor chip are electrically connected together through a gold bump, and the semiconductor chip and the electrical joint are sealed up with resin for manufacturing the semiconductor device. COPYRIGHT: (C)2003,JPO

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