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81. 发明专利

JP2013115345A Component built-in substrate, manufacturing method of the same, and component built-in substrate packaging body 有权
标题翻译：组件内置衬底，其制造方法和组件内置衬底包装体
公开(公告)号：JP2013115345A
公开(公告)日：2013-06-10
申请号：JP2011262217
申请日：2011-11-30
申请人： Fujikura Ltd , 株式会社フジクラ
发明人： ITOI KAZUHISA , OKAMOTO MASAHIRO
IPC分类号： H05K3/46
CPC分类号： H05K3/10 , H01L21/4857 , H01L23/367 , H01L23/3677 , H01L23/5389 , H01L24/19 , H01L2224/02311 , H01L2224/0401 , H01L2224/04105 , H01L2224/05569 , H01L2224/08237 , H01L2224/11312 , H01L2224/1132 , H01L2224/11334 , H01L2224/11416 , H01L2224/11418 , H01L2224/12105 , H01L2224/13009 , H01L2224/1329 , H01L2224/13294 , H01L2224/13309 , H01L2224/13311 , H01L2224/13313 , H01L2224/13316 , H01L2224/13324 , H01L2224/13339 , H01L2224/13344 , H01L2224/13347 , H01L2224/13355 , H01L2224/1336 , H01L2224/1339 , H01L2224/16225 , H01L2224/16238 , H01L2224/16503 , H01L2224/2929 , H01L2224/32225 , H01L2224/73201 , H01L2224/73251 , H01L2224/73253 , H01L2224/80203 , H01L2224/80447 , H01L2224/80903 , H01L2224/81192 , H01L2224/81203 , H01L2224/8185 , H01L2224/81862 , H01L2224/81907 , H01L2224/83192 , H01L2224/83203 , H01L2224/8349 , H01L2224/8385 , H01L2224/83862 , H01L2224/9211 , H01L2224/9221 , H01L2924/07811 , H01L2924/12042 , H01L2924/15153 , H05K1/0206 , H05K1/0207 , H05K1/186 , H05K3/0061 , H05K3/4602 , H05K3/4614 , H05K2201/0969 , H05K2201/10674 , Y10T29/49126 , H01L2924/00014 , H01L2924/0665 , H01L2924/0635 , H01L2924/069 , H01L2224/81 , H01L2224/83 , H01L2224/80 , H01L2224/16 , H01L2224/08 , H01L2224/32 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To ensure the adhesion between an electronic component and a heat conducting layer and improve heat radiation characteristics.SOLUTION: A component built-in substrate packaging body 100 is composed of a component built-in substrate 1 and a mounting substrate 2 where the component built-in substrate 1 is mounted. The component built-in substrate 1 includes a structure formed by collectively laminating second to fourth printed wiring base materials 20 to 40 and a coverlay film 3 by thermal compression bonding. In an opening 29 formed in a second resin base material 21 of the second printed wiring base material 20, a rear surface 91a of the electronic component 90 and a heat conducting layer 23A closely adhere and are incorporated therein while being fixed by an adhesive layer 9 through a pore 23B. Bumps 49 are formed on the mounting surface 2a side of the fourth printed wiring base material 40. Through the heat conducting layer 23A contacting with the rear surface 91a of the electronic component 90 and thermal vias 24, heat of the electronic component 90 passes through the thermal vias and thermal wiring on the respective layers, travels from the bumps 49 to the mounting substrate 2 and is radiated on the mounting substrate 2.
摘要翻译：要解决的问题：为了确保电子部件和导热层之间的粘附，并且改善散热特性。解决方案：组件内置基板封装体100由安装有内置基板1的内置基板1和安装基板2构成。组件内置基板1包括通过热压接而将第二至第四印刷布线基底材料20至40和覆盖膜3共同层叠形成的结构。在形成在第二印刷布线基材20的第二树脂基材21中的开口29中，电子部件90的后表面91a和导热层23A紧密地粘合并且被粘合层9固定通过孔23B。凸起49形成在第四印刷布线基材40的安装表面2a侧。通过与电子部件90的后表面91a接触的导热层23A和热通孔24，电子部件90的热量通过各层上的热通孔和热布线从凸块49行进到安装基板2并辐射在安装基板2上。（C）2013年，JPO和INPIT

82. 发明专利

JP2013518432A Ic die or dual career for joining the wafer to wafer tsv 审中-公开
公开(公告)号：JP2013518432A
公开(公告)日：2013-05-20
申请号：JP2012551156
申请日：2010-12-17
申请人：日本テキサス・インスツルメンツ株式会社 , テキサスインスツルメンツインコーポレイテッド
发明人：好美高橋 , ムルツザマスード , ダンラジブ , エスチャウハンサティエンデュラ
IPC分类号： H01L25/065 , H01L21/301 , H01L21/60 , H01L23/14 , H01L23/32 , H01L25/07 , H01L25/18
CPC分类号： H01L21/6836 , C09J5/06 , C09J2203/326 , C09J2205/302 , H01L21/561 , H01L21/565 , H01L21/76898 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/6834 , H01L2221/68381 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/81001 , H01L2224/81191 , H01L2224/81203 , H01L2224/81801 , H01L2224/83191 , H01L2224/83192 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01043 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/181 , H01L2924/19041 , H01L2924/20105 , H01L2224/81 , H01L2924/00 , H01L2224/05552
摘要：シリコン貫通ビア（ＴＳＶ）ウエハを用いてスタックされた電子的部品を形成する方法が、第１ディボンデング温度を有する第１接着性材料（２０６）を用いてＴＳＶウエハ（２０２）の上側に第１キャリアウエハ（２０５）を搭載することを含む。ＴＳＶウエハは、その下側から薄くされて薄くされたＴＳＶウエハ（２０２'）を形成する。第１ディボンデング温度より高い第２ディボンデング温度を有する第２接着性材料（２０７）を用いて、ＴＳＶウエハ（２０２'）の下側に第２キャリアウエハ（２１５）が搭載される。薄くされたＴＳＶウエハ（２０２'）はそれから第１キャリアウエハ（２０５）を取り除くため、前記第１ディボンデング温度を超える温度まで加熱される。スタックされた電子的部品を形成するため、少なくとも１つの個片化されたＩＣダイが、薄くされたＴＳＶウエハの上面上に形成されたＴＳＶダイに結合される。

83. 发明专利

JP2013030534A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013030534A
公开(公告)日：2013-02-07
申请号：JP2011164045
申请日：2011-07-27
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： NAKAMURA NOBUYUKI , MURAMOTO TAKUYUKI , TSUKAMOTO TAKEO
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L23/481 , H01L21/76898 , H01L24/13 , H01L24/14 , H01L25/0657 , H01L2224/13009 , H01L2224/13021 , H01L2224/1412 , H01L2224/14181 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To solve the problem in which, if an insulating film is embedded in a groove of a high aspect ratio at a high coverage characteristic, a slit-like void is formed on its surface, and, when it is flattened by CMP, a composition used at CMP, a removed object after polishing, and other residue are easy to remain in the void, which residue is possibly to be a cause of occurrence of dust in a step thereafter.SOLUTION: On a first main surface of a substrate 1, a first groove 2T which is in a ring shape in top view is formed. A first insulating film 2a is formed on the entire first main surface. The first insulator film is embedded in the first groove while a void having a depth reaching the inner part of the first groove from the surface of the first insulating film 2a is left. A second insulating film is formed on the first insulating film so as to fill the void. Flattening is performed down to the height of the substrate surface by chemical-mechanical polishing method while the first insulating film and the second insulating film are left in the first groove.
摘要翻译：解决的问题为了解决在绝缘膜嵌入到高覆盖特性的高纵横比的槽中的情况下，在其表面上形成狭缝状空隙的问题，并且当其被CMP平坦化，在CMP上使用的组合物，抛光后的被除去物体等残留物易于残留在空隙中，此后残留物可能成为灰尘发生的原因。解决方案：在基板1的第一主表面上，形成在顶视图中呈环形的第一凹槽2T。第一绝缘膜2a形成在整个第一主表面上。第一绝缘膜被嵌入第一槽中，而留下从第一绝缘膜2a的表面到达第一槽的内部的深度的空隙。在第一绝缘膜上形成第二绝缘膜以填充空隙。当第一绝缘膜和第二绝缘膜留在第一槽中时，通过化学机械抛光方法将基底表面的高度进行平坦化。版权所有（C）2013，JPO＆INPIT

84. 发明专利

JP2012256846A Manufacturing method of semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2012256846A
公开(公告)日：2012-12-27
申请号：JP2012039946
申请日：2012-02-27
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： ONO KENTA
IPC分类号： H01L21/304 , B23K26/00 , B23K26/06 , B23K26/36 , H01L21/3205 , H01L21/768 , H01L23/522
CPC分类号： H01L21/304 , H01L21/30625 , H01L21/6835 , H01L21/6836 , H01L21/76898 , H01L23/3128 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L25/0657 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , H01L2224/0345 , H01L2224/03912 , H01L2224/0401 , H01L2224/05166 , H01L2224/05572 , H01L2224/05647 , H01L2224/11002 , H01L2224/11009 , H01L2224/11462 , H01L2224/11622 , H01L2224/11849 , H01L2224/13009 , H01L2224/13021 , H01L2224/13023 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/14156 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/81815 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014 , H01L2924/12042 , H01L2924/12044 , H01L2924/14335 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/1438 , H01L2924/15311 , H01L2924/01047 , H01L2924/00 , H01L2224/05552
摘要： PROBLEM TO BE SOLVED: To reduce contamination of a substrate derived from a LTHC film.SOLUTION: A manufacturing method of a semiconductor device comprises the steps of: sticking a first principal surface of a substrate to a support substrate via a photo-thermal conversion film; and removing the photo-thermal conversion film exposed on the support substrate. This manufacturing method further includes the steps of: forming a photo-thermal conversion film on the support substrate; sticking a semiconductor substrate to the support substrate so that the photo-thermal conversion film extends to the outside from the semiconductor substrate; performing contamination prevention processing for the photo-thermal conversion film; and separating the support substrate and the semiconductor substrate.
摘要翻译：要解决的问题：减少由LTHC膜衍生的底物的污染。解决方案：半导体器件的制造方法包括以下步骤：通过光热转换膜将衬底的第一主表面粘附到支撑衬底; 并除去暴露在支撑基板上的光热转换膜。该制造方法还包括以下步骤：在支撑基板上形成光热转换膜; 将半导体衬底粘附到支撑衬底，使得光热转换膜从半导体衬底延伸到外部; 对光热转换膜进行污染防止处理; 并分离支撑基板和半导体基板。版权所有（C）2013，JPO＆INPIT

85. 发明专利

JP2012209497A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2012209497A
公开(公告)日：2012-10-25
申请号：JP2011075402
申请日：2011-03-30
申请人： Elpida Memory Inc , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立超エル・エス・アイ・システムズ
发明人： SHIGESANE YASUYUKI , YOKO HIDEYUKI , IDE AKIRA
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L23/481 , G11C5/025 , G11C5/063 , H01L24/13 , H01L24/14 , H01L25/0657 , H01L2224/0401 , H01L2224/05567 , H01L2224/13009 , H01L2224/13021 , H01L2224/13025 , H01L2224/13082 , H01L2224/13111 , H01L2224/13144 , H01L2224/13155 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/00013 , H01L2924/00014 , H01L2924/01029 , H01L2924/13091 , H01L2924/15311 , H01L2924/01047 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/05552
摘要： PROBLEM TO BE SOLVED: To stabilize a power supply voltage that is supplied to a controlled chip, relating to a stacked semiconductor device that uses a through electrode.SOLUTION: The semiconductor device includes an interposer IP to which a substrate power supply terminal 91V is provided, an interface chip IF where a surface bump FB is provided on one surface, with a rear surface bump BB provided on the other surface, and a core chip CC connected to the interface chip IF. The positions in plan view, viewed along stacking direction of the surface bump FB and the rear surface bump BB, connected to the substrate power supply terminal 91V, being provided to the interface chip IF, as well as a through electrode TSV1 connecting them, agree among others, with an array pitch P2 of the rear surface bumps BB for signal being shorter than an array pitch P1 of them. Since a power supply can be supplied to the core chip from the interposer IP straight, a power supply voltage that is supplied to the core chip can be stabilized.
摘要翻译：要解决的问题：为了稳定提供给受控芯片的电源电压，涉及使用通孔的层叠半导体器件。解决方案：半导体器件包括设置有基板电源端子91V的插入器IP，在一个表面上设置表面凸块FB的接口芯片IF，在另一个表面上设置有后表面凸块BB，和连接到接口芯片IF的核心芯片CC。连接到基板电源端子91V的连接到基板电源端子91V的表面凸块FB和后表面凸块BB的堆叠方向的平面图中的位置被设置到接口芯片IF，以及连接它们的贯通电极TSV1一致其中，具有用于信号的后表面凸块BB的阵列间距P2比它们的阵列间距P1短。由于可以从插入器IP直线向核心芯片提供电源，所以提供给芯片的电源电压可以稳定。版权所有（C）2013，JPO＆INPIT

86. 发明专利

JP2012209424A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2012209424A
公开(公告)日：2012-10-25
申请号：JP2011074001
申请日：2011-03-30
申请人： Tokyo Electron Ltd , 東京エレクトロン株式会社
发明人： NAKAO MASARU , HARADA MUNEO , IIDA ITARU , YAMAGUCHI EIJI
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0346 , H01L2224/0401 , H01L2224/05551 , H01L2224/0557 , H01L2224/05573 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/11002 , H01L2224/11332 , H01L2224/11505 , H01L2224/13009 , H01L2224/13076 , H01L2224/13082 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13294 , H01L2224/13339 , H01L2224/8184 , H01L2224/81986 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014 , H01L2924/01029 , H01L2924/12042 , H01L2224/03 , H01L2224/11 , H01L2224/05552 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of easily realizing formation of a through electrode at a chip and connection between the through electrodes.SOLUTION: A plurality of semiconductor substrates are prepared in which a through hole that penetrates between main surfaces is formed and the through hole is filled with a porous conductor. The plurality of semiconductor substrates are stacked with the porous conductors packed in the through hole being aligned. A conductor ink containing granular conductor is introduced into the porous conductor of the plurality of semiconductor substrates having been stacked. The plurality of stacked semiconductor substrates are baked.
摘要翻译：要解决的问题：提供一种制造半导体器件的方法，该半导体器件能够容易地实现芯片上的通孔的形成和贯通电极之间的连接。解决方案：制备多个半导体衬底，其中形成在主表面之间穿透的通孔，并且通孔填充有多孔导体。堆叠多个半导体衬底，其中填充在通孔中的多孔导体被对准。将含有粒状导体的导体墨导入堆叠的多个半导体基板的多孔导体中。多个层叠的半导体基板被烘烤。版权所有（C）2013，JPO＆INPIT

87. 发明专利

JP5018270B2 Semiconductor stack and a semiconductor device using the same 有权
标题翻译：空值
公开(公告)号：JP5018270B2
公开(公告)日：2012-09-05
申请号：JP2007164605
申请日：2007-06-22
申请人：パナソニック株式会社
发明人：佳子松田 , 和岐深田
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/10 , H01L2224/13 , H01L2224/13009 , H01L2224/16145 , H01L2224/16225 , H01L2224/9202 , H01L2924/07802 , H01L2924/15787 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor laminate structure which is excellent in connection reliability, has high productivity and can achieve thinning by using a conductive resin, a semiconductor device using it and their manufacturing method. SOLUTION: The semiconductor laminate structure 1 for which at least a first semiconductor chip 10 having a first wiring electrode and a second semiconductor chip 11 having a second wiring electrode are laminated includes at least the first semiconductor chip 10 connected with the second semiconductor chip 11 in a lamination direction and provided with a first conductive via 10d connected with a prescribed first wiring electrode and filled with a conductive resin and the second semiconductor chip 11 connected with the first semiconductor chip 10 in the lamination direction and provided with a second conductive via 11d connected with a prescribed second wiring electrode and filled with the conductive resin. The first conductive via 10d and the second conductive via 11d facing each other are electrically connected through a conductive connector 12. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：为了提供一种连接可靠性优异的半导体层叠结构体，具有高生产率，并且可以通过使用导电树脂，使用它的半导体器件及其制造方法来实现变薄。解决方案：至少具有第一布线电极的第一半导体芯片10和具有第二布线电极的第二半导体芯片11的半导体层叠结构1至少包括与第二半导体连接的第一半导体芯片10 芯片11在层叠方向上设置有与规定的第一布线电极连接并填充有导电树脂的第一导电通孔10d，以及第二半导体芯片11，其在层叠方向上与第一半导体芯片10连接并且设置有第二导电通孔11d与规定的第二布线电极连接并填充有导电树脂。第一导电通孔10d和彼此面对的第二导电通孔11d通过导电连接器12电连接。版权所有：（C）2009，JPO＆INPIT

88. 发明专利

JP2012064891A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012064891A
公开(公告)日：2012-03-29
申请号：JP2010209998
申请日：2010-09-17
申请人： Toshiba Corp , 株式会社東芝
发明人： INOUE SATOSHI , KANDA KAZUE , SHIMIZU ARITAKE
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L24/97 , G11C5/025 , H01L21/76898 , H01L22/22 , H01L23/3107 , H01L23/481 , H01L23/4951 , H01L23/49575 , H01L24/16 , H01L24/48 , H01L25/0657 , H01L2224/13009 , H01L2224/4826 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/06596 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01058 , H01L2924/01075 , H01L2924/01078 , H01L2924/014 , H01L2924/1203 , H01L2924/13091 , H01L2924/1431 , H01L2924/1434 , H01L2924/1438 , H01L2924/181 , H01L2224/81 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To provide a structure that deactivates a defective semiconductor chip including a stacked chip while reducing manufacturing cost.SOLUTION: A semiconductor device comprises a stacked chip 20 and deactivation circuits 44. The stacked chip 20 includes a stack of a plurality of semiconductor chips 21 each having a plurality of semiconductor substrates 33 and a plurality of through electrodes 31 formed in the plurality of semiconductor substrates 33. The plurality of through electrodes 31 are electrically connected one another. Each of the deactivation circuits 44 is provided on the plurality of semiconductor chips 21, and deactivates a defective semiconductor chip.
摘要翻译：要解决的问题：提供一种降低制造成本的同时使包括堆叠芯片的缺陷半导体芯片失效的结构。解决方案：半导体器件包括堆叠芯片20和去激活电路44.堆叠芯片20包括多个半导体芯片21的堆叠，每个半导体芯片21具有多个半导体衬底33和形成在多个半导体衬底多个半导体基板33.多个贯通电极31彼此电连接。每个失活电路44设置在多个半导体芯片21上，并且使半导体芯片失效。版权所有（C）2012，JPO＆INPIT

89. 发明专利

JPWO2010032729A1 半導体装置の製造方法有权
公开(公告)号：JPWO2010032729A1
公开(公告)日：2012-02-09
申请号：JP2010529764
申请日：2009-09-15
申请人：国立大学法人東京大学 , 国立大学法人東京大学
发明人：大場　隆之 , 隆之大場
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L21/76898 , B81B2207/07 , B81C1/00238 , B81C2201/019 , B81C2203/0792 , H01L23/481 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2221/68345 , H01L2221/68377 , H01L2224/13009 , H01L2224/16145 , H01L2224/32145 , H01L2224/83005 , H01L2224/8385 , H01L2224/9202 , H01L2225/06541 , H01L2225/06589 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10252 , H01L2924/10253 , H01L2924/14 , H01L2924/1461 , H01L2924/15788 , H01L2924/00014 , H01L2924/00
摘要：主面側に半導体集積回路を有する複数の半導体チップが形成された半導体基板を積層し、異なる層の前記半導体基板を構成する前記半導体チップ同士を信号伝達可能に接続し、その後前記半導体チップ部分を個片化する半導体装置の製造方法であって、第1の半導体基板及び第2の半導体基板を準備する第1工程と、前記第2の半導体基板を薄型化する第2工程と、薄型化された前記第2の半導体基板の主面と反対側の面を、絶縁層を介して前記第1の半導体基板の主面に固着する第3工程と、薄型化された前記第2の半導体基板に、前記第2の半導体基板の主面から主面と反対側の面に貫通するビアホールを形成する第4工程と、前記ビアホールを介して、前記第1の半導体基板の前記半導体チップと前記第2の半導体基板の前記半導体チップとの間の信号伝達を可能にする接続部を形成する第5工程と、を有することを特徴とする。

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