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81. 发明专利

JPS57208046A IMAGE DISPLAY APPARATUS 失效
公开(公告)号：JPS57208046A
公开(公告)日：1982-12-21
申请号：JP9499481
申请日：1981-06-18
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： INOHARA SHIZUO , MASUDA MITSUYA , TAKUHARA SADAHIRO , UEDA MINORU , YAMAMOTO HIROSUKE
IPC分类号： H04N9/12
摘要： PURPOSE:To increase the video resolution of an image display screen by increasing the sampling frequency of a video signal included in an original-color signal (a signal of three original colors R, G and B) by using a signal obtained by sampling the pulses within the time if a horizontal one picture element as a control signal, which is applied to a control electrode. CONSTITUTION:Sampling pulses (aR, aG, aB... nR, nG, nB) of this invetion, the width of which is 1/3 the width of conventional sampling pulses (a, b...n) (indicated by broken lines in the figure), are produced continuously, in that order, for each picture element. Here, the frequency of the sampling pulses (aR, bR...nR; aG, bG...nG. or aB, bB...nB) for each of original-color signals R, G, and B is the same as that of conventional sampling pulses, while their width is 1/3 the width of the conventional sampling pulses. Besides, the sampling frequency of the R, G, B video signal component becomes three times that of the conventional one.

82. 发明专利

JPS5737927A Signal deciding and switching circuit 失效
标题翻译：信号决定和切换电路
公开(公告)号：JPS5737927A
公开(公告)日：1982-03-02
申请号：JP11215080
申请日：1980-08-13
申请人： Matsushita Electric Ind Co Ltd
发明人： TAKUHARA SADAHIRO , KAWASHIMA KAZUMI , FUJITA MASAAKI
IPC分类号： H03J7/00 , G06F19/00 , H03J7/18 , H03K17/60 , H03K17/62 , H03K19/173 , H04B3/00
CPC分类号： H03K19/1732
摘要： PURPOSE:To decrease the number of pins of an integrated circuit, by transferring the signal between the digital and analog integrated circuits via a two-way signal line. CONSTITUTION:When a digital input signal (d) of a terminal 14 of a digital integrated circuit 1 is at L level, a signal output circuit is turned on. Then a signal (e') of an input/output terminal 27 is set at H level. An input signal deciding circuit 12 is turned on, and an output signal (c') of a terminal 13 is set at L level. An output (f') of a voltage comparator 32 is set at H level since the H-level signal (e') of an input/ output terminal 30 of an analog integrated circuit 2 is set higher than the comparison voltage (m) of the comparator 32. Then a signal (g) equal to an analog input signal (a) of the terminal 3 is delivered via signal changeover circuits 20 and 23. When the signal (d) is set at H level, the circuit 15 is turned off. Then the output voltage of an impedance converter 31 of a voltage comparator 5 is applied to the comparator 32. This voltage is lower than the voltage (m), so the signal (f') of the comparator 32 is set at L level to deliver the DC voltage (g) of a certain level to the terminal 24. At the same time, a signal (c') having the same waveform as the output voltage of the converter is delivered to the terminal 13 via the circuit 12.
摘要翻译：目的：通过双向信号线在数字和模拟集成电路之间传输信号，减少集成电路的引脚数。构成：当数字集成电路1的端子14的数字输入信号（d）处于L电平时，信号输出电路导通。然后，输入/输出端子27的信号（e'）被设置为H电平。输入信号判定电路12导通，端子13的输出信号（c'）设定为L电平。由于模拟集成电路2的输入输出端子30的H电平信号（e'）被设定为高于模拟集成电路2的比较电压（m），所以将电压比较器32的输出（f'）设定为H电平比较器32.然后，经由信号切换电路20和23传送等于端子3的模拟输入信号（a）的信号（g）。当信号（d）被设置为H电平时，电路15转动关闭然后将电压比较器5的阻抗转换器31的输出电压施加到比较器32上。该电压低于电压（m），因此比较器32的信号（f'）设定为L电平以传送与端子24的一定电平的直流电压（g）。同时，具有与转换器的输出电压相同波形的信号（c'）经由电路12被传送到端子13。

83. 发明专利

JPS56156988A REFRESH SYSTEM FOR NONVOLATILE MEMORY 失效
公开(公告)号：JPS56156988A
公开(公告)日：1981-12-03
申请号：JP6015680
申请日：1980-05-06
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： TAKUHARA SADAHIRO , KAWASHIMA KAZUMI , UEDA MINORU , YAMAMOTO HIROSUKE , HOSOKAWA TAKUHISA , FURUTA MASAO
IPC分类号： G11C17/00 , G06F11/14 , G11C11/34 , G11C16/02 , G11C16/26
摘要： PURPOSE:To continue refresh routines at the reclosing of a power source by performing refreshing according to the storage contents of the specific areas assigned to the refresh buffers and refresh address memories of ROMs. CONSTITUTION:The area of an address 0 of an MNMOS memory 3 is assigned to a refresh buffer memory, and a refresh address signal is stored therein. On the other hand, the area of an address F is assigned to a refresh address memory, and stores a refresh address and a refresh routine state. With this constitution if the F area routine state is read out by way of an I/O 10 at the reclosing of the power source, the instruction including jump operation in succession to the refresh routine cycle of readout, write-in, erasing, output and input modes is formed by the microcomputer 11 of a control circuit 2.

84. 发明专利

JPS56116321A VOLTAGE COMPARATOR 失效
公开(公告)号：JPS56116321A
公开(公告)日：1981-09-12
申请号：JP2026380
申请日：1980-02-19
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： KAWASHIMA KAZUMI , UEDA MINORU , TAKUHARA SADAHIRO , YAMAMOTO HIROSUKE
IPC分类号： H03J5/02 , H03J3/18
摘要： PURPOSE:To reject flicker phenomenon, by inputting compared voltage through common connection of one input of two voltage comparison circuits of a channel selector of a TV receiver and connecting another input to the both ends of a resistance for comparison through given comparison voltage. CONSTITUTION:The neutral point voltage of a preset variable resistor 21 is applied to the base of a transistor TR29 connected to a constant current circuit 28, the emitter of TR29 is connected to the base of TR30, temperature compensation is made at TR30, and the voltage is applied to a constant current circuit 32 via a resistance 31. The both ends of the resistance 31 are respectively connected to the (-) terminal of voltage comparison circuits 33, 34, the (+) terminals of the circuits 33, 34 are connected in common and a voltage VRef to be compared is applied to it. The output of the circuits 33, 34 is connected to the base of switching TRs 43, 49 of opposite polarity via a resistance, and the collector of the TRs 43, 39 are connected to the output terminal 27 respectively bia resistance 40, 41. Taking the voltage between the (-) terminal and ground of the circuits 33, 34, as VR1, VR2 respectively, TRs 39, 43 are off when VR2

85. 发明专利

JPS5687917A ADJUSTER OF TUNING VOLTAGE 失效
公开(公告)号：JPS5687917A
公开(公告)日：1981-07-17
申请号：JP16507179
申请日：1979-12-18
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HOSOKAWA TAKUHISA , UEDA MINORU , KAWASHIMA KAZUMI , TAKUHARA SADAHIRO , YAMAMOTO HIROSUKE , YAMATANI MAKOTO
IPC分类号： H03J5/02 , H03J7/24 , H03J7/28
摘要： PURPOSE:To enable to make short the time when both voltages are in coincidence by increasing the count speed of a counter at the change-over to the preset mode, by the constitution that one clock pulse can equivalently be used as a plurality of clock pulses. CONSTITUTION:When a switch 13 is switched from the normal mode to the preset mode, the location applying clock pulse to the counter 2 is moved to the input terminal of high rank digit in the counter 2, and the counting is made by further increasing the weight than original clock pulse. One clock pulse generated at the clock pulse generating circuit 1 can equivalently be used as a plurality of clock pulses.

86. 发明专利

JPS55165021A CHANNEL SELECTION UNIT 失效
公开(公告)号：JPS55165021A
公开(公告)日：1980-12-23
申请号：JP7272379
申请日：1979-06-08
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： KAWASHIMA KAZUMI , UEDA MINORU , TAKUHARA SADAHIRO , YAMAMOTO HIROSUKE
IPC分类号： H03J5/02
摘要： PURPOSE:To prevent the channel selection at detuning state, by adding the tuning voltage information from the microcomputer muCM and the clock pulse to the D/A conversion circuit and adding the clock pulse to muCM as driving clock after frequency division. CONSTITUTION:The tuning voltage information from the muCM39 is fed to the D/A converter 41, and the clock pulse from the oscillator 49 is fed to the converter 41. The converter 41 coverts the tuning voltage information into the pulse train having the pulse width information according to the tuning voltage, based on the clock pulse to add it to the LPF45, and the output is fed to the varactor diode of the tuner 46 for channel selection. In this case, the clock pulse from the oscillator 49 is frequency-divided at the variable frequency divider 51 and it is fed to the muCM39 as driving clock. Thus, the repetitive frequency of the clock pulse of the converter 41 is taken greater than the clock repetitive frequency of the muCM39 and the time constant of LPF45 can be decreased without increasing the ripple component of the output, allowing the unit to prevent from being entered into channel selection at detuning state.

87. 发明专利

JPS55165020A CHANNEL SELECTION UNIT 失效
公开(公告)号：JPS55165020A
公开(公告)日：1980-12-23
申请号：JP7272279
申请日：1979-06-08
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： KAWASHIMA KAZUMI , UEDA MINORU , TAKUHARA SADAHIRO , YAMAMOTO HIROSUKE
IPC分类号： H03J5/00 , H03J5/02
摘要： PURPOSE:To prevent the malfunction at power supply switch switching, by providing the power supply clear circuit with the channel selection unit controlled with the microcomputer muCM to control the operation time of the muCM and the memory. CONSTITUTION:The muCM39 reads out the channel selection information stored in the CMOS memory 40 by the operation of the switch of the key matrix 37 and performs channel selection operation via the D/A conversion and the band latch circuit 41. The output signal of the power supply clear circuit 53 is fed to the muCM39 and memory 40 to turn on the power supply turning on switch to the muCM39 and the memory 40 so that the output signal of muCM and memory is risen with a given time delayed than the operation time of muCM and memory. Further, control is made with the output signal of the circuit 53 so that the output signal falls before the operation of muCM and memory is stopped through the opening of the power supply switch. Thus, the malfunction of muCM and memory due to noise at power supply switching can be prevented.

88. 发明专利

JPS5398724A DRIVING UNIT FOR TELEVISION RECEIVER 失效
公开(公告)号：JPS5398724A
公开(公告)日：1978-08-29
申请号：JP1380177
申请日：1977-02-09
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： TAKUHARA SADAHIRO , YAMAMOTO HIROSUKE
IPC分类号： H04N3/18 , H04N3/16
摘要： PURPOSE:To surely operate the horizontal oscillating circuit, to increase the reliability, and to simplify the circuit constitution, by commonly using the drive transistor as the blocking oscillating transistor.

89. 发明专利

JPS5159229A TEREBIJONJUZOKINO SUIHEIHENKOKEIKAIRO 失效
公开(公告)号：JPS5159229A
公开(公告)日：1976-05-24
申请号：JP13410974
申请日：1974-11-20
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： SHIBANO NAOKI , NAKADA TOSHIAKI , TAKUHARA SADAHIRO
IPC分类号： H04N3/18

90. 发明专利

JPH0454432B2 失效
公开(公告)号：JPH0454432B2
公开(公告)日：1992-08-31
申请号：JP23365382
申请日：1982-12-29
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： UEDA MINORU , YOSHIDA TOSHIFUMI , TAKUHARA SADAHIRO , MASUDA MITSUYA , INOHARA SHIZUO
IPC分类号： G09G3/30 , H04N5/68

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