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71. 发明专利

JP2005317751A Inversely conductive semiconductor device and its manufacturing method 有权
标题翻译：反向导电半导体器件及其制造方法
公开(公告)号：JP2005317751A
公开(公告)日：2005-11-10
申请号：JP2004133698
申请日：2004-04-28
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： AONO SHINJI , YAMAMOTO AYA , TAKAHASHI HIDEKI
IPC分类号： H01L29/06 , H01L21/322 , H01L21/331 , H01L21/336 , H01L21/8234 , H01L27/04 , H01L27/06 , H01L27/088 , H01L29/08 , H01L29/739 , H01L29/76 , H01L29/78
CPC分类号： H01L21/263 , H01L29/0834 , H01L29/7397
摘要： PROBLEM TO BE SOLVED: To provide an inversely conductive semiconductor device in which an insulating gate bipolar transistor and a commutation diode improved in a recovery characteristic are integrally formed on a substrate. SOLUTION: In an inversely conductive semiconductor device, an insulating gate bipolar transistor and a commutation diode are integrally formed on a substrate comprised of a first conductive semiconductor. The commutation diode includes a second conductive base layer and a first conductive base layer of the insulating gate bipolar transistor and is configured using an emitter electrode on one surface of the substrate as an anode electrode and a collector electrode on another surface of the substrate as a cathode electrode, and a low lifetime area wherein a lifetime of a carrier is shortened in comparison with another first conductive base layer, is formed in a portion of the first conductive base layer. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供一种反向导电的半导体器件，其中绝缘栅双极晶体管和恢复特性得到改善的整流二极管一体地形成在衬底上。解决方案：在反向导电半导体器件中，绝缘栅双极晶体管和整流二极管一体地形成在由第一导电半导体构成的衬底上。换向二极管包括绝缘栅双极晶体管的第二导电基极层和第一导电基极层，并且使用基板的一个表面上的发射电极作为阳极电极和在基板的另一表面上的集电极电极作为阴极电极和低寿命区域，其中与第一导电基底层相比，载体的寿命缩短，形成在第一导电基底层的一部分中。版权所有（C）2006，JPO＆NCIPI

72. 发明专利

JP3713490B2 Semiconductor device 有权
公开(公告)号：JP3713490B2
公开(公告)日：2005-11-09
申请号：JP2003039765
申请日：2003-02-18
申请人：株式会社東芝
发明人：川明夫中 , 村和敏中 , 口雄介川 , 代知子末
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/08 , H01L29/10 , H01L29/78
CPC分类号： H01L29/7835 , H01L29/0847 , H01L29/1083 , H01L29/7801

73. 发明专利

JP2005302696A Top-emission organic electroluminescent element and its manufacturing method 有权
标题翻译：最大排放有机电致发光元件及其制造方法
公开(公告)号：JP2005302696A
公开(公告)日：2005-10-27
申请号：JP2005002476
申请日：2005-01-07
申请人： Samsung Sdi Co Ltd , 三星エスディアイ株式会社
发明人： SEO CHANG-SU , PARK MOON-HEE
IPC分类号： H05B33/26 , H01L29/08 , H01L51/50 , H01L51/52 , H05B33/02 , H05B33/10 , H05B33/14 , H05B33/22
CPC分类号： H01L51/5218 , H01L2251/5315
摘要： PROBLEM TO BE SOLVED: To provide a top-emission organic electroluminescent element wherein a galvanic corrosion phenomenon generated in an interface between a transparent electrode material and a metal material is suppressed, and to provide a manufacturing method for this. SOLUTION: This top-emission organic electroluminescent element comprises a reflection film layer 210a on a substrate 100, a first electrode layer 210 provided with a metal-silicide layer 210b and a transparent electrode layer 210c, an organic film layer 230 containing at least one or more luminous layers, and a second electrode layer. The top-emission organic electroluminescent element is provided with the metal-silicide layer between the reflection film layer used as the first electrode layer and the transparent electrode layer so that the corrosion phenomenon due to a galvanic effect generated in the interface of the reflection film layer and the transparent electrode layer is suppressed for stabilizing the contact resistance between layers to realize uniform luminance between pixels and a screen of high quality. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供抑制在透明电极材料和金属材料之间的界面中产生的电偶腐蚀现象的顶发射有机电致发光元件，并提供其制造方法。解决方案：该顶部发射有机电致发光元件包括在基板100上的反射膜层210a，设置有金属硅化物层210b的第一电极层210和透明电极层210c，含有至少一个或多个发光层和第二电极层。顶部发射有机电致发光元件在用作第一电极层的反射膜层和透明电极层之间设置有金属硅化物层，使得由于在反射膜层的界面中产生的电偶效应引起的腐蚀现象并且抑制透明电极层以稳定层之间的接触电阻，以实现像素之间的均匀亮度和高质量的屏幕。版权所有（C）2006，JPO＆NCIPI

74. 发明专利

JP3705919B2 Semiconductor device and a method of manufacturing the same 失效
公开(公告)号：JP3705919B2
公开(公告)日：2005-10-12
申请号：JP5342798
申请日：1998-03-05
申请人：三菱電機株式会社
发明人：勝光中村
IPC分类号： H01L29/78 , H01L21/331 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/739
CPC分类号： H01L29/0696 , H01L21/3221 , H01L29/0834 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/456 , H01L29/66348 , H01L29/66734 , H01L29/7397 , H01L29/7811 , H01L29/7813
摘要： A gate electrode is provided to fill up a trench while covering its opening. Assuming that WG represents the diameter (sectional width) of a head portion of the gate electrode located upward beyond a P-type base layer and an N -type emitter diffusion layer , WT represents the diameter (sectional width) of an inner wall of a linearly extending portion of the trench and WC represents the distance between the boundary (the inner wall of the trench 300) between a gate oxide film and the P-type base layer and an end surface of the gate electrode located upward beyond the trench in a section of the trench , relation of either WG>=1.3.WT or WC>=0.2 mum holds between these dimensions.

75. 发明专利

JP2005217237A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005217237A
公开(公告)日：2005-08-11
申请号：JP2004022817
申请日：2004-01-30
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： TOMINAGA HISAAKI , ODAJIMA KEITA , MATSUMOTO NARUHITO , YAMAMURO MASAMICHI
IPC分类号： H01L29/72 , H01L21/331 , H01L29/08 , H01L29/732
CPC分类号： H01L29/66287 , H01L29/0821 , H01L29/7322
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device improving high frequency characteristics without deteriorating collector/emitter withstand voltage (VCEO) characteristics, and to provide its manufacturing method.
SOLUTION: A second SIC layer in contact with an intrinsic base region is provided just under the intrinsic base region, and a first SIC layer having higher impurity concentration than the second SIC layer is provided just under the second SIC layer. An improvement of an fT characteristic is ensured by narrowing a collector width by making use of the first SIC layer and restraining the Kirk effect, and cutting a lower end of the intrinsic base region by making use of the second SIC layer. Further, two SIC layers having different depths can be formed with only one heat treatment by adopting an impurity having a larger diffusion coefficient than that of the second SIC layer as an impurity of the first SIC layer.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种提高高频特性的半导体器件，而不会降低集电极/发射极耐受电压（VCEO）特性，并提供其制造方法。解决方案：在本征基区下方提供与本征基区接触的第二SIC层，并且在第二SIC层的正下方提供具有比第二SIC层更高的杂质浓度的第一SIC层。通过利用第一SIC层缩小集电体宽度并抑制Kirk效应，并利用第二SIC层切割本征基区的下端来确保fT特性的改善。此外，通过采用具有比第二SIC层更大的扩散系数的杂质作为第一SIC层的杂质，可以仅形成具有不同深度的两个SIC层。版权所有（C）2005，JPO＆NCIPI

76. 发明专利

JP3681942B2 Method of manufacturing a bipolar transistor 有权
公开(公告)号：JP3681942B2
公开(公告)日：2005-08-10
申请号：JP37388199
申请日：1999-12-28
申请人：松下電器産業株式会社
发明人：啓一村山 , 学柳原 , 毅田中 , 武司福井
IPC分类号： H01L29/73 , H01L21/328 , H01L21/331 , H01L29/06 , H01L29/08 , H01L29/205 , H01L29/737
CPC分类号： H01L29/66318 , H01L29/0692 , H01L29/0817 , H01L29/7371

77. 发明专利

JP3681741B2 Semiconductor device 有权
公开(公告)号：JP3681741B2
公开(公告)日：2005-08-10
申请号：JP2004001886
申请日：2004-01-07
申请人：新電元工業株式会社
发明人：雅人三川 , 伸治九里 , 瑞枝北田 , 大島　　宏介 , 寛明宍戸 , 昌弘栗山
IPC分类号： H01L27/06 , H01L21/8234 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/47 , H01L29/66712 , H01L29/7395 , H01L29/7802 , H01L29/7809
摘要： A semiconductor device having high ruggedness is provided. The distance Wm 2 between buried regions 44a, positioned at the bottoms of different base diffusion regions 17a and face each other is set smaller than the distance Wm 1 between buried regions 44a positioned at the bottom of the same base diffusion region 17a (Wm 1 > Wm 2 ). An avalanche breakdown occurs under the bottom of the base diffusion region 17a, and the avalanche current is not passed through a high resistance part immediately under the source diffusion region 21 in the base diffusion region 17a, providing high withstand strength against destruction.

78. 发明专利

JP2005197287A Semiconductor device and its fabrication process 审中-公开
标题翻译：半导体器件及其制造工艺
公开(公告)号：JP2005197287A
公开(公告)日：2005-07-21
申请号：JP2003435265
申请日：2003-12-26
申请人： Rohm Co Ltd , ローム株式会社
发明人： TAKAISHI AKIRA
IPC分类号： H01L21/265 , H01L21/336 , H01L29/06 , H01L29/08 , H01L29/40 , H01L29/78
CPC分类号： H01L29/0634 , H01L21/26586 , H01L29/0873 , H01L29/1095 , H01L29/407 , H01L29/66712 , H01L29/7802
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of enhancing the withstand voltage, and to provide its fabrication process. SOLUTION: On an N + conductivity type silicon substrate 2 forming a drain region, a semiconductor layer 13 having a so-called super junction structure formed thereon is provided. The semiconductor layer 13 includes an N - conductivity type drift layer 3 and a P - conductivity type reduced surface layer 9 wherein the drift layer 3 and the reduced surface layer 9 are arranged to appear alternately in the direction parallel with the silicon substrate 2. The drift layer 3 creeps under the reduced surface layer 9 (between the silicon substrate 2 and the reduced surface layer 9). More specifically, the reduced surface layer 9 is separated from the silicon substrate 2 by the drift layer 3 and does not touch the silicon substrate 2. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供能够提高耐压的半导体器件，并提供其制造工艺。解决方案：在形成漏区的N + 导电型硅衬底2上，提供了形成有所谓的超结结构的半导体层13。半导体层13包括导电型漂移层3和P - 导电型还原表面层9，其中漂移层3和还原表面层9被布置在与硅衬底2平行的方向上交替出现。漂移层3在还原表面层9（硅衬底2和还原表面层9之间）之下蠕变。更具体地，还原表面层9通过漂移层3与硅衬底2分离，并且不与硅衬底2接触。版权所有（C）2005，JPO＆NCIPI

79. 发明专利

JP2005191247A Semiconductor substrate and semiconductor device using the same 审中-公开
标题翻译：半导体基板和使用该半导体器件的半导体器件
公开(公告)号：JP2005191247A
公开(公告)日：2005-07-14
申请号：JP2003430267
申请日：2003-12-25
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： OTANI KINYA
IPC分类号： H01L21/336 , H01L29/06 , H01L29/08 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/0834 , H01L29/0847 , H01L29/7397 , H01L29/7802
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor substrate for manufacturing a vertical type device, in which a low ON-resistance of a vertical type MOSFET or the like is maintained, whereas a needed OFF breakdown strength can be ensured.
SOLUTION: This semiconductor substrate is constituted, such that a high density arsenic layer 12 having a thickness of 0.5 to 3.0 μm is inserted in between a high density phosphorus layer 11 constituting the drain of the vertical-type MOSFET and an n-type drift layer 13. Thus, since the high-density arsenic layer 12 functions as a barrier layer which prevents phosphorus from spreading, from the high density phosphorus layer 11 to the n-type drift layer 13, the spread of a depletion layer, when turning off in the vertical-type MOSFET is ensured to enhance an OFF breakdown strength, and also the low ON resistance can be maintained.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于制造垂直型MOSFET等的低导通电阻的垂直型器件的半导体衬底，而可以确保所需的OFF击穿强度。解决方案：该半导体衬底被构造成使得在构成垂直型MOSFET的漏极的高密度磷层11和n-型晶体管的漏极之间插入厚度为0.5至3.0μm的高密度砷层12，因此，由于高密度砷层12作为防止磷从高浓度磷层11扩散到n型漂移层13的阻挡层发挥消耗层的扩散，因此当确保在垂直型MOSFET中的关断以提高OFF击穿强度，并且还可以保持低导通电阻。版权所有（C）2005，JPO＆NCIPI

80. 发明专利

JP2005183936A Bipolar transistor 有权
标题翻译：双极晶体管
公开(公告)号：JP2005183936A
公开(公告)日：2005-07-07
申请号：JP2004323844
申请日：2004-11-08
申请人： Sharp Corp , シャープ株式会社
发明人： TWYNAM JOHN
IPC分类号： H01L21/331 , H01L29/08 , H01L29/20 , H01L29/737 , H01L29/76
CPC分类号： H01L29/7606 , H01L29/0817 , H01L29/2003 , H01L29/7371
摘要： PROBLEM TO BE SOLVED: To provide a bipolar transistor provided with a structure wherein a performance thereof is not influenced by a sheet resistance of a base layer and capable of exhibiting a high current gain even in a high-frequency region.
SOLUTION: In the bipolar transistor, there are provided a collector layer 104 consisting of an n-type semiconductor and an emitter layer 106 consisting of an n-type semiconductor which is provided on this collector layer 104. A gate layer 107 for injecting p-type carriers (holes) into the emitter layer 106 is provided on the emitter layer 106. A p-type carrier retaining layer 105 is formed between the collector layer 104 and the emitter layer 106. The p-type carrier retaining layer 105 temporarily retains the p-type carriers that are injected from the gate layer 107 into the emitter layer 106 and are diffused in the emitter layer 106 and reach the p-type carrier retaining layer 105.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有结构的双极晶体管，其中其性能不受基极层的薄层电阻的影响，并且即使在高频区域中也能够呈现高的电流增益。解决方案：在双极晶体管中，提供了由n型半导体和由设置在该集电极层104上的n型半导体构成的发射极层106构成的集电极层104.用于在发射极层106上设置注入p型载流子（空穴）到发射极层106.在集电极层104和发射极层106之间形成p型载流子保持层105.p型载流子保持层105 暂时保留从栅极层107注入到发射极层106中并在发射极层106中扩散并到达p型载流子保持层105的p型载流子。（C）2005，JPO＆NCIPI

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