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71. 发明专利

JPS61276032A INFORMATION PROCESSING DEVICE 失效
公开(公告)号：JPS61276032A
公开(公告)日：1986-12-06
申请号：JP11903585
申请日：1985-05-31
申请人： MATSUSHITA ELECTRIC IND CO LTD , SANYO ELECTRIC CO , MITSUBISHI ELECTRIC CORP , SHARP KK
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , ASANO HAJIME , SHIMIZU MASAHISA , MIURA HIROKI , SHIMA KENJI , KOMORI NOBUFUMI , MIYATA SOICHI , MATSUMOTO SATOSHI
IPC分类号： G06F15/82 , G06F9/38 , G06F9/44
摘要： PURPOSE:To shorten instruction executing time by changing the tag data of a preceding token, having a delaying function, making unnecessary a dummy token by a compiler, neglecting the sequence characteristic of the token, executing the delaying function and making simple the compiler constitution. CONSTITUTION:When the contents of the instruction code field of the received token correspond to the delaying instruction, the contents of the tag field are made into +1, written into the tag field again, and transmitted through a network 6 in the processing element to a program memory part 3. The memory part 3 reads the program memory with the contents of the destination field of the received token as the address, updates the contents of the second - fourth fields of the first word of the received token and sends to the network 6 again. At the network 6, when the contents of the destination field of the received token correspond to the outside of the present processing element, the contents are transmitted through the token network to a corresponding element, and except for it, the action is repeated again.

72. 发明专利

JPS61262956A DATA TRANSMITTING DEVICE 失效
公开(公告)号：JPS61262956A
公开(公告)日：1986-11-20
申请号：JP10667085
申请日：1985-05-17
申请人： SHARP KK , MATSUSHITA ELECTRIC IND CO LTD , SANYO ELECTRIC CO , MITSUBISHI ELECTRIC CORP
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , MIYATA SOICHI , MATSUMOTO SATOSHI , ASANO HAJIME , SHIMIZU MASAHISA , MIURA HIROKI , KOMORI NOBUFUMI , SHIMA KENJI
IPC分类号： G06F5/06 , G06F13/00 , G06F15/16
摘要： PURPOSE:To improve a data throughput for branching and joining by using a free-running shift register to secure the wired OR connection between the control signal outputs of two transfer control circuits at the branching and joining parts and sending an answer back to the transfer control circuit at a preceding stage. CONSTITUTION:An input data transmission line 100, an output data transmission line 200, a branch data transmission line 300 and a joining data transmission line 700 are formed with a free-running register containing plural data latches and transfer control circuits (C elements). The data latches are set between the lines 100 and 200 as well as lines 100 and 300. The outputs of elements C of the latches are sent to the control input of the elements C in a wired OR connection form. While the data latches are also set between the lines 100 and 200 as well as lines 200 and 700. Then the outputs of elements C of the latches are sent to the control input of the element C with wired OR connection. In such a way, the data throughput is improved for the branching and the joining.

73. 发明专利

JPS5971554A Digital circuit simulator 失效
标题翻译：数字电路仿真器
公开(公告)号：JPS5971554A
公开(公告)日：1984-04-23
申请号：JP18200182
申请日：1982-10-15
申请人： Matsushita Electric Ind Co Ltd , Mitsubishi Electric Corp , Sanyo Electric Co Ltd , Sharp Corp
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , OKAMOTO TOSHIYA , TOKURA TAKESHI , SHIMIZU MASAHISA , KAMIMURA KAZUO
IPC分类号： G06F11/25 , G06F11/26 , G06F17/50 , G06F19/00
CPC分类号： G06F11/261
摘要： PURPOSE:To attain parallel simulation of logical elements operated in parallel, by reading out a data from a career data storage means to attain operating processing, when the data is set from an input set means to an execution control means. CONSTITUTION:The data relating to each element included in a digital circuit is set to an execution control unit 31 at each element, and the career data before a noted generation is stored in a function memory 32. The unit 31 and the memory 32 are connected directly, an input/output subsystem 2, operation processing units 4a-4b, and execution control means 3a-3c are connected individually via a common bus 1. When the input data is set from the subsystem 2 to the unit 31, the data relating to the element to which all data are set is given to the units 4a-4b corresponding to the unit 31 reading out the career data from the memory 32, and the units 4a-4b performs te logical operation of the corresponding elements.
摘要翻译：目的：为了实现并行操作的逻辑元件的并行仿真，通过从职业数据存储装置读取数据以获得操作处理，当数据从输入集合装置设置到执行控制装置时。构成：将包含在数字电路中的每个元素的数据设置在每个元件处的执行控制单元31，并且将所述生成之前的职业数据存储在功能存储器32中。单元31和存储器32被连接直接地，输入/输出子系统2，操作处理单元4a-4b和执行控制装置3a-3c经由公共总线1分别连接。当输入数据从子系统2被设置到单元31时，数据相关向与从存储器32读出职业数据的单元31对应的单元4a-4b给予设定了所有数据的单元，并且单元4a-4b执行相应元件的逻辑运算。

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