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    • 75. 发明专利
    • MEMORY
    • JPH06266606A
    • 1994-09-22
    • JP5394393
    • 1993-03-15
    • HITACHI LTD
    • NISHIYAMA KAZUHIDEDAIJIYOU SHIGETOKUMAI HIROYUKIINOUE MASAYUKI
    • G06F12/00
    • PURPOSE:To read storage information at high speed. CONSTITUTION:An address latch 3 latches a previous row address. When the latch row address 105 of the address latch 3 differs from a row address 102, a non-coincidence detection circuit 4 outputs a non-coincidence signal 106 showing that they are non-coincident. At that time, row unit information 107 which is read from a memory array 2 passes through a row information latch 5 and information designated by a row address 103 is selected by a selector 7. A CPU reads information 204. From an output control circuit 8 after it becomes valid, and the row address 102 is latched by the address latch 3. When the row address 102 coincides with the latch row address 105, the non-coincidence signal 106 showing non-coincidence is obtained. The row information latch 5 inhibits row unit information 107 from the memory array 2 and transmits valid information which is latched by it to the selector 7. The CPU immediately reads it.