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61. 发明专利

JPH03254538A CRYPTOGRAPHIC SYSTEM 失效
公开(公告)号：JPH03254538A
公开(公告)日：1991-11-13
申请号：JP5337190
申请日：1990-03-05
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SHIMIZU AKIHIRO
IPC分类号： G09C1/00 , H04L9/06 , H04L9/22
摘要： PURPOSE:To attain cryptographic processing at a faster speed than a speed of a conventional system by applying parallel processing to a division data resulting from dividing an input plain sentence data comprising plural bits by means of variable bit rotation and addition, and further applying rotation processing to the entire data. CONSTITUTION:In a cryptographic system in which an input plain sentence data comprising plural bits is processed by using an intermediate key obtained from processing a secret key data comprising of plural bits to obtain a cryptographic data, a key processing section 10 processes a 128-bit secret key K to calculate a 256-bit intermediate key KS. The intermediate key KS consists of parallel data KS , KS , KS , KS in 64-bit (8-bit) each. Moreover, the key processing section 10 calculates a 4X4 matrix R using bit rotation number being an integral number of 3-10 as its elements. The cryptographic processing is implemented after the end of key processing. A cryptographic processing section 20 uses the 256-bit intermediate key KS and the matrix R, ciphers a 126-bit plain sentence data Y in parallel processing to obtain a cryptographic sentence Y'.

62. 发明专利

JPH03192383A ONE BLOCK SUBSTITUTION METHOD 失效
公开(公告)号：JPH03192383A
公开(公告)日：1991-08-22
申请号：JP26529890
申请日：1990-10-04
申请人： TELEDYNE IND
发明人： ROSUROTSUPU MITSUTENSAARU
IPC分类号： G09C1/00 , H04L9/06 , H04L9/22
摘要： PURPOSE: To convert an arbitrary plain text block into a related ciphered block by finding out a first matrix of two equations, each of which expresses one module 2 addition of two n-bit binary plain text blocks, to obtain a ciphered n-bit block. CONSTITUTION: A plain text word is sent to an address of a memory I. This operation corresponds to selection of a word Xk- Ps other than θ from a column 3. Order data of a plain text word K-Ps is sent to an adder and is added to Ps. A new order number is sent to its address in a memory II. Contents of this address are added to the plain text word by module 2 to obtain a ciphered word Xk-s in a column 1. When the plain text word is θ, its ciphered test picture is the same. Order data is added by two adders, namely, a carry (C) adder and a least significant bit(LSB) adder.

63. 发明专利

JPH0394329A RANDOM NUMBER GENERATOR 失效
公开(公告)号：JPH0394329A
公开(公告)日：1991-04-19
申请号：JP23253589
申请日：1989-09-07
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MURAKAMI HIRONORI
IPC分类号： G06F7/58 , H04K1/00 , H04K1/06 , H04L9/22 , H04N7/167 , H04N7/169
摘要： PURPOSE:To obtain a random number string with high secrecy by selecting the output of exclusive OR between the outputs of two random number generating circuits and the output of the 2nd random number generating circuit in accordance with the detected result of a protection circuit, inputting the selected results to a comparator and executing necessary shifting operation based upon the compared result. CONSTITUTION:Exclusive OR operation between the output of the 1st random number generating circuit (shift register for generating random numbers to be successively shifted) 5 and the output of the 2nd random number generating circuit (shift register for generating random number to be shifted in each block of a random number string) 6 is executed in each bit. The output of the exclusive OR and the output of the shift register 6 for generating random numbers to be shifted in each block are switched by the protection circuit 9 and the switched result is applied to a comparator 10 to shift the shift register 5 for generating random number to be successively shifted. Consequently, a random number with high secrecy can be obtained.

64. 发明专利

JPH02249333A PRIVACY TELEPHONE SET 失效
公开(公告)号：JPH02249333A
公开(公告)日：1990-10-05
申请号：JP7020089
申请日：1989-03-22
申请人： SHARP KK
发明人： HIRAIDE JUNJI , TADA JUNJI
IPC分类号： H04L9/22 , H04L9/06 , H04L9/14
摘要： PURPOSE:To eliminate the need for revision of a key in the case of revising a cipher by providing a pseudo random signal generating circuit, a storage circuit, a control means and a conversion circuit respectively to a transmission side and a reception side, providing a ciphering key setting means, a ciphering circuit to the transmission side and a decoding circuit to the reception side. CONSTITUTION:First and 2nd pseudo random signal generating circuits 1, 2 at the transmission side an the reception side employ shift registers having a feedback path capable of switching and generate various different pseudo random signals by revising the feedback path and the initial value. On the other hand, 1st and 2nd storage circuits 3, 3 store the plural sets of initial values and feedback path setting data of the pseudo random signal generating circuits 1, 2, read the storage content of the storage circuit 3 in response to the setting of a ciphering key setting means 5 to set the pseudo ran dom signal generating circuits 1, 2, thereby generating different pseudo random signals. Then the reception side selects the pseudo random signal from the pseudo random signal generating circuits 1, 2 to make the pseudo random signal identical to the transmission side and the reception side. Thus, it is not required to replace the cipher ing key itself and the setting and revision of the key are attained easily and freely.

65. 发明专利

JPH02105737A ARITHMETIC CIRCUIT 失效
公开(公告)号：JPH02105737A
公开(公告)日：1990-04-18
申请号：JP25847688
申请日：1988-10-14
申请人： NEC CORP
发明人： CHOKAI YOSHITAKA
IPC分类号： G09C1/00 , H04L9/18 , H04L9/22
摘要： PURPOSE:To reduce the number of registers used for an arithmetic circuit and, at the same time, the processing time of the circuit by using the arithmetic circuit as a de-scrambler and only using exclusive ORs(EX-OR) as arithmetic functions. CONSTITUTION:The data of the 14th bit of a shift register 12 are extracted by means of a bit extraction circuit 17 and inputted to the lowest-order bit of a shift register 13. Then the EX-OR of the shift registers 12 and 13 is taken and inputted to a general purpose register 14. Then the EX-OR of the registers 14 and 13 is taken and inputted to the register 14 after 1-bit input data 18 are inputted to the shift register 13 through a selection circuit 15. Then the shift register is shifted by one bit and the 1-bit input data 18 are inputted to the lowest-order bit of the register 12. Then the lowest-order bit of the register 14 are outputted to an output side 19. The above-mentioned processes are repeated. Therefore, the number of registers to be used and processing time can be reduced.

66. 实用新型

JPH01113440U 失效
公开(公告)号：JPH01113440U
公开(公告)日：1989-07-31
申请号：JP698388
申请日：1988-01-22
IPC分类号： H04L7/00 , H04L9/22 , H04L9/02

67. 发明专利

JPS63294115A NONLINEAR RANDOM SERIES GENERATOR 失效
公开(公告)号：JPS63294115A
公开(公告)日：1988-11-30
申请号：JP11270588
申请日：1988-05-11
申请人： COMMUNICATIONS SATELLITE CORP
发明人： RIN NAN RII , FUARUHADO HEMATEI
IPC分类号： G06F7/58 , H03K3/84 , H04L9/22 , H04L9/26

68. 发明专利

JPS63290427A CRYPTOGRAPHIC DEVICE 失效
公开(公告)号：JPS63290427A
公开(公告)日：1988-11-28
申请号：JP12624087
申请日：1987-05-22
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： SATO YOSHIO
IPC分类号： H04L9/12 , H04L9/22
摘要： PURPOSE:To prevent a key to decode a block cryptographic code from being found out by applying scrambling to a cryptographic data including a frame synchronizing bit so as to prevent the frame synchronizing bit in a communication data. CONSTITUTION:A plane data inputted from an input terminal 10 is subject to cryptographic processing by a block cryptographic coding section 11 for each frame of prescribed length according to the frame timing generated by a frame timing generating section 14 and added with a frame synchronizing bit representing the section of a frame by a synchronizing bit addition section 12 and the result is outputted. A cryptographic data added with the frame synchronizing bit is subject to scrambling by a self-synchronizing type scrambler 13 and the result is outputted to an output terminal 15. On the other hand, a self-synchronizing type descrambler of a decoding section applies descrambling to decode a data the same as the output data of the addition section 12.

69. 发明专利

JPS63222537A RANDOM NUMBER SCRAMBLING SYSTEM 失效
公开(公告)号：JPS63222537A
公开(公告)日：1988-09-16
申请号：JP5724587
申请日：1987-03-12
申请人： FUJITSU LTD
发明人： OISO MITSUO
IPC分类号： G06F7/58 , G09C1/00 , H04L9/22 , H04L9/24
摘要： PURPOSE:To generate a random number difficult to analysis by a simple method by generating a random number through the synthesis between an output of interposition at random and a random number before random interposition. CONSTITUTION:Pseudo random number generators 1, 2, a buffer section 3, and a synthesizer transposing the output of the pseudo random number generator 1 by the output of the pseudo random number generator 2 at random and synthesizing the result with the output of the pseudo random number generator 1, are provided. That is, the output transposing the output from the pseudo random number generator 1 at random by using the output from the pseudo random number generator 2 via the buffer section 3 and the random number before the random transposition are synthesized to generate a random number thereby suppressing the use of the same random number to the utmost. Thus, a random number offering difficulty in analysis is generated by the simple system.

70. 发明专利

JPS62287737A CIPHERING SYSTEM 失效
公开(公告)号：JPS62287737A
公开(公告)日：1987-12-14
申请号：JP13017986
申请日：1986-06-06
申请人： HITACHI LTD
发明人： IKEDA TETSUYA
IPC分类号： H04L9/06 , H04L9/14 , H04L9/22
摘要： PURPOSE:To improve the security of ciphering maintainability by using a ROM for a random pattern ciphered or decoded so as to change an address signal of the ROM depending on the content of the ciphered data. CONSTITUTION:A transmission data processing section 11 processes the sent data in the unit of one work or byte and a transmission data is fed to an exclusive OR circuit 12. The circuit 12 applies ciphering by applying exclusive OR between transmission data and a random data in the unit of one word or byte outputted from the random pattern ROM 14. The ciphered data is converted into a serial data by a parallel/serial conversion circuit 13 in this way and sent. Then the content of the ROM 14 applying ciphering is not decoded in accordance with the order of address. Thus, the confidentiality security for ciphering maintainability is improved.

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