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61. 发明专利

JPH0697432B2 失效
公开(公告)号：JPH0697432B2
公开(公告)日：1994-11-30
申请号：JP14067986
申请日：1986-06-17
IPC分类号： G06F7/487 , G06F7/52 , G06F7/53 , G06F7/533

62. 发明专利

JPH06290029A MULTIPLYING METHOD AND MULTIPLYING CIRCUIT 失效
公开(公告)号：JPH06290029A
公开(公告)日：1994-10-18
申请号：JP7316493
申请日：1993-03-31
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MINEMARU TAKAYUKI , TOYOKURA MAKI
IPC分类号： G06F7/533 , G06F7/52 , G06F17/10 , G06F15/31
摘要： PURPOSE:To provide a multiplying method and a multiplying circuit capable of executing multiplication without expanding circuit size too much even when the bit length of data is extended by coding both of a multiplier and a multiplicand by using Booth algorithm. CONSTITUTION:A multiplier 1 and a multiplicand 2 are respectively inputted to Booth coding means 3, 4. Four 4-bit parts expressing the absolute values of four 5-bit signals out of code signals 5, 6 obtained by coding the multiplier 1 and code signals 7, 8 obtained by coding the multiplicand 2 are inputted to a partial product generating means 9 and partial products 14 to 17 are outputted from the means 9 and inputted to a partial product adding means 18. On the other hand, code bits 10 to 13 expressing the codes of the code signals 5 to 8 are also inputted to the means 18 to control the addition/subtraction of the partial products 14 to 17. Addition/subtraction is executed by the means 18 and a product 19 is outputted.

63. 发明专利

JPH06208456A CPU WITH INTEGRATED MULTIPLICATION / ACCUMULATION UNIT 失效
公开(公告)号：JPH06208456A
公开(公告)日：1994-07-26
申请号：JP14731792
申请日：1992-06-08
申请人： NAT SEMICONDUCTOR CORP
发明人： RARUFU DABURIYU HAINZU , GEIRII DEI FUIRITSUPUSU , DONARUDO KEBIN KOBII , TOOMASU DABURIYU ESU TOMUSON
IPC分类号： G06F7/533 , G06F7/52 , G06F7/53 , G06F7/544 , G06F9/38 , G06F12/08
摘要： PURPOSE: To provide a multiplying/accumulating function in a short clock cycle. CONSTITUTION: A system memory 108 for storing data, a bus interface mechanism 110 provided in a CPU, and a system bus 106 which connects between arithmetic means, such as multiplication/accumulation units 104, etc., which perform arithmetic processing on retrieved data are provided and the CPU manages its internal register 112 used when the arithmetic means retrieve data in response to a program instruction specified by the CPU. The arithmetic means performs multiplication of two binary numbers with codes by using a corrected booth algorithm and, when the means perform the multiplication, reducing the cycle time and hardware conditions.

64. 发明专利

JPH06110658A ARITHMETIC DEVICE 失效
公开(公告)号：JPH06110658A
公开(公告)日：1994-04-22
申请号：JP25768892
申请日：1992-09-28
申请人： TOSHIBA CORP
发明人： KAI NAOYUKI
IPC分类号： G06F7/533 , G06F7/52 , G06F7/527 , G06F7/53 , G06F17/17 , G06T1/20 , G06T11/00 , G06F15/353 , G06F15/66
摘要： PURPOSE:To provide the arithmetic device which has a reduced circuit scale and high operating frequency by using a coded parallel multiplier. CONSTITUTION:This device is provided with a first arithmetic means (subtracter) 1 for calculating difference between integer data (s) and (d) with respect to two pieces of integer data (s) and (d) composed of the same number of bits and interpolating coefficient alpha, selecting means (selector) 3 for selectively holding either of the integer data (s) and (d), second arithmetic means (multiplier) 5 for multiplying the coded numbers of the interpolating coefficient alpha by that of the arithmetic result of the first arithmetic means 1, and third arithmetic means (adder) 7 for adding the arithmetic result of the second arithmetic means 5 to the output value of the selecting means 3. At the time of alpha =1/2, the integer data (s) are selected by the selecting means 3, and the arithmetic operation of (alpha-1)X(s-d)+s is performed as the entire arithmetic unit.

65. 发明专利

JPH06103031A MULTIPLYING CIRCUIT 失效
公开(公告)号：JPH06103031A
公开(公告)日：1994-04-15
申请号：JP25504892
申请日：1992-09-24
申请人： NEC CORP
发明人： KUSANO YOSHITAKA
IPC分类号： G06F7/533 , G06F7/508 , G06F7/52
摘要： PURPOSE:To reduce the energy consumption of the multiplying circuit in the case of handling the signal of a small absolute value as a multiplier or a multiplicand in the multiplying circuit for the complementary of '2' using the algorithm of a booth. CONSTITUTION:This circuit is provided with a multiplying circuit control part 40 for performing multiplication by shifting either one or both of the multiplier and multiplicand to the side of an MSB and shifting the other one to '0' when the absolute value of the multiplier or the multiplicand is small, and multiplying circuit control part 50 for shifting the multiplied result to the side of an LSB.

66. 发明专利

JPH05265715A 失效
公开(公告)号：JPH05265715A
公开(公告)日：1993-10-15
申请号：JP6295892
申请日：1992-03-19
IPC分类号： G06F7/533 , G06F7/506 , G06F7/52 , G06F7/544 , G06F17/10 , G06F15/31
摘要： PURPOSE:To shorten the delay time with an adder/multiplier which adds two data together and multiplies the result of this addition by one of both data. CONSTITUTION:A coding circuit 1 codes the data X based on the algorithm of a Booth for multiplication of both data K and X. A partial product sum circuit 4 operates a partial product from the data K based on the output value of the circuit 1 and obtains the sum total. The circuit 1 contains an addition circuit part 2 which adds together both data Y and X and a coding circuit 3. In such a constitution, the transmission delay time can be shortened.

67. 发明专利

JPH05216626A MULTIPLIER 失效
公开(公告)号：JPH05216626A
公开(公告)日：1993-08-27
申请号：JP1733992
申请日：1992-02-03
申请人： NEC CORP
发明人： OZAKI YASUSHI
IPC分类号： G06F7/533 , G06F7/52
摘要： PURPOSE:To increase the addition calculation speed of the partial product and to suppress the increase of the hardware scale by performing the double- precision multiplication by repeatedly multiplying the specific bits. CONSTITUTION:Multiplier Y between 2n-bit multiplicand X and multiplier Y is decoded by means of the secondary Booth's algorithm, inputted to the multiplier side of a partial product generation circuit, performing multiplication by means of a single precision multiplier where (n)X(n) bit (n is any natural number). The multiplier Y is expressed by the formula. The secondary Booth's algorithm formula for the multiplier Y is expressed by Ej=-2y2j+1+y2j+y2j-1. The decoder input to be decoded is switched by taking Ej=-2y2 j+1+y2j+y2j-1 as (y2j+1, y2j, y2j+1) and by taking Ej+n=-2y2j+1+n+y2j+n+y2j-1+n as (y2j+1+n, y2 j+n, y2j-1+n).

68. 发明专利

JPH0588854A PARTIAL PRODUCT PREPARING CIRCUIT AND MULTIPLYING CIRCUIT 失效
公开(公告)号：JPH0588854A
公开(公告)日：1993-04-09
申请号：JP24970091
申请日：1991-09-27
申请人： SANYO ELECTRIC CO
发明人： KANEKO KAZUNARI
IPC分类号： G06F7/533 , G06F7/52 , G06F7/53
摘要： PURPOSE:To make the multiplication fast by reducing the number of the constitu tion gates of a partial product preparing circuit used for a multiplying circuit using the Booth's algorithm and the redundant binary number. CONSTITUTION:This circuits are constituted of a transmission gate 6 to output a multiplicand X in accordance with a signal M1-1 to show + or -1 by (Y-1+Y0-2Y1) based on the Booth's algorithm, a transmission gate 8 to shift the multiplicand X to 1 bit higher order and output it in accordance with a signal M2-1 to show + or -2 by (Y-1+Y0-2Y1), and a P channel MOS to make the partial product output into 0 by the output of an OR gate 3 to detect 0 by (Y-1+Y0-2Y1). A signal P1-SGN, a signal M2-1 and a partial product output P1 to show the code of (Y-1+Y0-2Y1) are outputted to a redundant binary encoder.

69. 发明专利

JPH0553770A MULTIPLYING CIRCUIT USING SHIFT ADDITION SYSTEM 失效
公开(公告)号：JPH0553770A
公开(公告)日：1993-03-05
申请号：JP21885691
申请日：1991-08-29
申请人： SANYO ELECTRIC CO
发明人： KANEKO KAZUNARI
IPC分类号： G06F7/533 , G06F7/52 , G06F7/527
摘要： PURPOSE:To obtain a multiplying equipment being appropriate to an integrated circuit by simplifying circuit constitution in the multiplying circuit of a shift action system. CONSTITUTION:A multiplier is expressed by the number of a min. item in the shape of + or -an2 + or -an-12 + or -... a12+ or -a02 and an output signal from the output stage of a shift register corresponding to the respective items is added so as to obtain the multiplying output. When the multiplier is 30, for example, the multiplier is expressed as 2 -2 , the output of a first stage in the five-stage shift register 13 is inverted by an inverter 14 and the inversion output is added to the output of the fifth stage in the shift register 13 by a full adder circuit 15. In this case, DFF 16 for holding carry is made to be a set state by a set signal so that +1 is added to the inverted multiplicand so as to calculate the complement of two.

70. 发明专利

JPH051497B2 失效
公开(公告)号：JPH051497B2
公开(公告)日：1993-01-08
申请号：JP24098685
申请日：1985-10-28
申请人： TOSHIBA KK , TOSHIBA MAIKURO EREKUTORONIKUSU KK
发明人： SAKAGAMI KENJI
IPC分类号： G06F7/533 , G06F7/52 , G06F7/53

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