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61. 发明专利

JPS5936929A Fabrication of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS5936929A
公开(公告)日：1984-02-29
申请号：JP14870182
申请日：1982-08-25
申请人： Mitsubishi Electric Corp
发明人： SATOU SHINICHI
IPC分类号： H01L21/033 , H01L21/302 , H01L21/3065 , H01L21/768
CPC分类号： H01L21/76834 , H01L21/0337 , H01L21/302 , Y10S257/90
摘要： PURPOSE: To simultaneously form micro-miniaturized pattern and smoothed stepped portion simultaneously by leaving an insulating layer to the stepped portion of sharp edge of conductive layer obtained by physical etching while smoothening leaving insulating layer.
CONSTITUTION: A high precision wiring pattern is formed by applying physical etching to a polysilicon 3. After removing a photoresist mask4, a silicon oxide film 7 is formed in the thickness of 0.7μm over the entire part of the surface. The physical etching is then executed on the entire part of oxide film 7 under the C
3 F
3 plasma generated between the parallel electrodes. When the etching is continued until the oxide film 7 on the silicon 3 or oxide film 2 is removed, the silicon oxide film 7a remains at the stepped portion. Thereby, in case an insulating film 5 and an aluminum Al wiring 6 are formed thereon, problem of disconnection or short-circuit at the stepped portion is no longer generated.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：通过在通过物理蚀刻获得的导电层的锋利边缘的阶梯部分留下绝缘层同时形成微小型化图案和平滑台阶部分，同时平滑留下绝缘层。构成：通过对多晶硅3进行物理蚀刻形成高精度布线图案。去除光致抗蚀剂掩模4之后，在表面的整个部分上形成厚度为0.7μm的氧化硅膜7。然后在平行电极之间产生的C3F3等离子体的氧化膜7的整个部分上进行物理蚀刻。当继续蚀刻直到去除硅3或氧化物膜2上的氧化物膜7时，氧化硅膜7a保留在台阶部分。因此，在形成绝缘膜5和铝铝布线6的情况下，不再产生在阶梯部分处的断路或短路的问题。

63. 发明专利

JP2014195091A Method and device for improving salicide resistance on polycrystal silicon gate 有权
标题翻译：用于改善多晶硅栅的耐腐蚀性的方法和装置
公开(公告)号：JP2014195091A
公开(公告)日：2014-10-09
申请号：JP2014095009
申请日：2014-05-02
申请人： Intel Corp , インテル・コーポレーション
发明人： JAN CHIA-HONG , TSAI JULIE A , YANG SIMON , GHANI TAHIR , WHITEHILL KEVIN A , KEATING STEVEN J , MYERS ALAN
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L21/8234 , H01L29/41 , H01L29/423 , H01L29/49
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/82345 , H01L29/4933 , H01L29/66575 , Y10S257/90
摘要： PROBLEM TO BE SOLVED: To provide a gate electrode improving salicide resistance in a polycrystal silicon gate smaller than 0.20 μm.SOLUTION: A gate electrode includes a polycrystalline silicon gate layer disposed on a substrate, a first spacer disposed adjacently to both sides of the gate layer, a second spacer disposed adjacently to the first spacer, and a conductive layer 260 disposed on the gate layer. The first spacer and the second spacer include sidewalls which are parallel with each other along the entire height thereof. The gate layer, the first spacer and the second spacer have the equal height, and the conductive layer extends laterally on the first spacer but does not extend on a sidewall of the gate layer and the second spacer.
摘要翻译：要解决的问题：提供一种在多晶硅栅极中改善硅化物电阻的栅电极，其小于0.20μm。解决方案：栅极包括设置在衬底上的多晶硅栅极层，与栅极两侧相邻设置的第一间隔物层，与第一间隔物相邻设置的第二间隔件，以及设置在栅极层上的导电层260。第一间隔件和第二间隔件包括沿其整个高度彼此平行的侧壁。栅极层，第一间隔物和第二间隔物具有相等的高度，并且导电层在第一间隔物上横向延伸，但不延伸在栅极层和第二间隔物的侧壁上。

65. 发明专利

JP2014075557A Manufacturing method for semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：JP2014075557A
公开(公告)日：2014-04-24
申请号：JP2012223643
申请日：2012-10-05
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： MAEKAWA TAKASHI , MIHARA TATSUYOSHI
IPC分类号： H01L21/8234 , H01L27/088
CPC分类号： H01L21/823468 , H01L21/26513 , H01L21/266 , H01L21/31116 , H01L21/823418 , H01L21/823462 , H01L29/0615 , H01L29/36 , H01L29/66477 , H01L29/6653 , H01L29/66553 , Y10S257/90 , Y10S438/90
摘要： PROBLEM TO BE SOLVED: To improve performance and reliability of a semiconductor device.SOLUTION: After an insulating film IL6 and other insulating film are sequentially formed on a semiconductor substrate SUB so as to cover gate electrodes GE1, GE2, and GE3, a sidewall spacer SW1 is formed on a side surface IL6a of the insulating film IL6 by etching back the other insulating film. The sidewall spacer SW1 on the side surface IL6a of the insulating film IL6 corresponding to the side walls of the gate electrodes GE1 and GE2 is removed, and the sidewall spacer SW1 on the side surface IL6a of the insulating film IL6 corresponding to the side wall of the gate electrode GE3 remains. Thereafter, the sidewall spacer SW1 and the insulating film IL6 are etched back, and the sidewall spacer made of the insulating film IL6 is formed on the side walls of the gate electrodes GE1, GE2, and GE3. The width of the sidewall spacers on the side walls of the gate electrodes GE1 and GE2 is smaller than the width of the sidewall spacer on the side wall of the gate electrode GE3.
摘要翻译：要解决的问题：提高半导体器件的性能和可靠性。解决方案：在绝缘膜IL6和其它绝缘膜依次形成在半导体衬底SUB上以覆盖栅电极GE1，GE2和GE3之后，侧壁间隔物通过蚀刻另一绝缘膜，在绝缘膜IL6的侧表面IL6a上形成SW1。除去与栅电极GE1，GE2的侧壁对应的绝缘膜IL6的侧面IL6a上的侧壁间隔物SW1，与绝缘膜IL6的侧壁对应的绝缘膜IL6的侧面IL6a上的侧壁间隔物SW1 栅电极GE3残留。此后，侧壁间隔物SW1和绝缘膜IL6被回蚀刻，并且由绝缘膜IL6制成的侧壁间隔物形成在栅电极GE1，GE2和GE3的侧壁上。栅电极GE1和GE2的侧壁上的侧壁间隔物的宽度小于栅电极GE3的侧壁上的侧壁间隔物的宽度。

66. 发明专利

JP5255207B2 Memory array and a method of manufacturing the same 有权
公开(公告)号：JP5255207B2
公开(公告)日：2013-08-07
申请号：JP2006508591
申请日：2004-01-08
申请人：スパンションエルエルシー
发明人：タズリーンカマル , マークティーラムスベイ , ヒデヒコシライワ , フレッドケーティーチュング
IPC分类号： H01L21/336 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L27/115 , H01L2224/48247 , H01L2224/85464 , H01L2924/01012 , H01L2924/01019 , H01L2924/01021 , H01L2924/01057 , H01L2924/01087 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , Y10S257/90 , H01L2924/00
摘要： The present invention relates to a memory array comprising a substrate and a plurality of bitlines having contacts and a plurality of wordlines intersecting the bitlines. A protective spacer is used to separate the bitline contacts from the wordlines adjacent to the bitline contacts to prevent damage caused during the formation of the bitline contacts. The present invention also relates to a method of forming the memory array.

67. 发明专利

JP5179692B2 Semiconductor memory device and a method of manufacturing the same 有权
公开(公告)号：JP5179692B2
公开(公告)日：2013-04-10
申请号：JP2002256120
申请日：2002-08-30
申请人：富士通セミコンダクター株式会社 , スパンションエルエルシー , アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドAdvanced Micro Devices Incorporated
发明人：秀樹小森 , 久幸島田 , ユー・サン , 博幸木下
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L21/823425 , H01L21/823468 , H01L27/115 , H01L27/11568 , Y10S257/90
摘要： A drain (7) comprises a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

68. 发明专利

JP5132943B2 Semiconductor device 有权
公开(公告)号：JP5132943B2
公开(公告)日：2013-01-30
申请号：JP2007013747
申请日：2007-01-24
申请人：パナソニック株式会社
发明人：晋赤松
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/768 , H01L23/532 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L27/11 , H01L21/823412 , H01L21/823468 , H01L21/823807 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/7833 , H01L29/7843 , Y10S257/90 , Y10S438/981

69. 发明专利

JP4519442B2 Mos transistor and a method of manufacturing the same 有权
公开(公告)号：JP4519442B2
公开(公告)日：2010-08-04
申请号：JP2003358405
申请日：2003-10-17
申请人：三星電子株式会社Samsung Electronics Co.,Ltd.
发明人：宰圭李
IPC分类号： H01L21/28 , H01L29/78 , H01L21/336 , H01L21/8234 , H01L27/088 , H01L29/417 , H01L29/423 , H01L29/49
CPC分类号： H01L29/66628 , H01L29/41775 , H01L29/41783 , Y10S257/90

70. 发明专利

JP2009522819A Structures and methods for fabricating high density mosfet circuit having a contact lines of different heights 有权
公开(公告)号：JP2009522819A
公开(公告)日：2009-06-11
申请号：JP2008549683
申请日：2007-01-09
申请人：インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation
发明人：ズー，ホイロン
IPC分类号： H01L21/8234 , H01L21/28 , H01L21/768 , H01L21/8244 , H01L23/522 , H01L27/08 , H01L27/088 , H01L27/11 , H01L29/78 , H01L29/786
CPC分类号： H01L21/28052 , H01L21/76889 , H01L21/76895 , H01L27/11 , H01L27/1104 , H01L29/4933 , H01L29/665 , H01L29/78 , H01L2924/0002 , Y10S257/90 , Y10S257/92 , H01L2924/00
摘要：【課題】異なる高さのコンタクト線を有する高密度ＭＯＳＦＥＴ回路を製造するための構造、方法などを提示すること。
【解決手段】このＭＯＳＦＥＴ回路は、コンタクト線（５００、１３００）と、コンタクト線（５００、１３００）の近くに位置するゲート（３１０、１２１０）とを含む。コンタクト線（５００、１３００）は、ゲート（３１０、１２１０）の高さよりも低い高さを含む。このＭＯＳＦＥＴ回路はさらに、ゲート（３１０、１２１０）の近くに位置するゲート・スペーサ（７１０、７１５、１６１０、１６１５）を含み、コンタクト線（５００、１３００）とゲート（３１０、１２１０）との間のコンタクト線（５００、１３００）の近くに位置するコンタクト線スペーサを含まない。
【選択図】図１

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