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61. 发明专利

JPS63261441A DATA STORAGE DEVICE 失效
公开(公告)号：JPS63261441A
公开(公告)日：1988-10-28
申请号：JP9645587
申请日：1987-04-20
申请人： SANYO ELECTRIC CO
发明人： TANAKA KAZUYUKI , MIURA HIROKI , SHIMIZU MASAHISA
IPC分类号： G06F12/00 , G06F9/44 , G06F15/82
摘要： PURPOSE:To independently read out a specific element in a data set by dividing a pointer memory storing address information into plural blocks and allocating the blocks to respective programs. CONSTITUTION:A data packet holds a set name of a required data set and an environment number and loads the set name to a counter in a pointer address memory (pam). Then, the contents of the memory (pam) are read out by using the output of the counter as an address and the contents obtained by adding the environment number to the read out contents are latched to registers r1, r2. The content of the blocked pointer memories pm1, pm2 are read out by using the contents of the registers r1, r2 as addresses and latched to an address register (ar) of a data memory (dm). The contents of the memory (dm) are read out by using the contents of the register (ar) as an address. Thus, a specific data element included in plural sets can be read out by applying its set name.

62. 发明专利

JPS61190397A VOICE SYNTHESIZATION 失效
公开(公告)号：JPS61190397A
公开(公告)日：1986-08-25
申请号：JP3181485
申请日：1985-02-20
申请人： SANYO ELECTRIC CO
发明人： SHIMIZU MASAHISA , KITAMURA TORU
IPC分类号： G10L13/00 , G10L19/08

63. 发明专利

JPS5916500A Digital sound recording and reproducing method 失效
标题翻译：数字声音记录和再现方法
公开(公告)号：JPS5916500A
公开(公告)日：1984-01-27
申请号：JP12659382
申请日：1982-07-19
申请人： Sanyo Electric Co Ltd
发明人： SHIMIZU MASAHISA , HARA HIDEJI
IPC分类号： G11B20/10 , H04S1/00
CPC分类号： H04S1/00
摘要： PURPOSE:To attain the reproduction in matching with the purpose of the listener, by amplifying and reproducing each sound source signal recorded digitally for each sound source at each sound source of each speaker. CONSTITUTION:Sound source signals from plural sound sources 1-4 are sound recorded digitaly at the same time for every sound sources 1-4. The intensity of musical sound vectors S1, S2 at a listening point 18 with musical sound vectors A1-A4 of the sound sources 1-4 recorded digitally for the sound sources 1-4 is calculated depending on the relation of position of the listening point 18 and the sound images 1'-4' and the relation of position of speakers 19, 20 and the listening point 18, and the result is amplified and reproduced at the sound sources 1-4 for the specakers 19, 20. A reproducing signal is outputted from the speakers 19, 20.
摘要翻译：目的：为了与收听者的目的相一致地实现再现，通过放大和再现每个扬声器的每个声源处的每个声源以数字方式记录的每个声源信号。构成：来自多个声源1-4的声源信号对于每个声源1-4同时对数字进行声音记录。根据收听点18的位置的关系来计算在音源1-4处以数字记录的声源1-4的音乐声音矢量A1-A4的收听点18处的音乐声音矢量S1，S2的强度和声像1'-4'以及扬声器19,20和收听点18的位置的关系，并且结果在声源1-4处被放大和再现，用于拍摄者19,20。再现信号是从扬声器19,20输出。

64. 发明专利

JPS56102898A ELECTRONIC MUSICAL INSTRUMENT 失效
公开(公告)号：JPS56102898A
公开(公告)日：1981-08-17
申请号：JP513280
申请日：1980-01-18
申请人： SANYO ELECTRIC CO
发明人： MORI NORIAKI , SHIMIZU MASAHISA
IPC分类号： G10H7/08 , G10H1/20 , G10H7/00

65. 发明专利

JPH03127289A DATA PROCESSOR 失效
公开(公告)号：JPH03127289A
公开(公告)日：1991-05-30
申请号：JP26662389
申请日：1989-10-13
申请人： SANYO ELECTRIC CO
发明人： SHIMIZU MASAHISA
IPC分类号： G06F15/82
摘要： PURPOSE:To increase the packet waiting processing speed by simultaneously executing detection of a pair of operand packets and packet write to a waiting memory in the packet waiting mechanism of a data driven processor. CONSTITUTION:The waiting mechanism of the data driven processor consists of a 2-port memory 21, an address generator 22, a comparator 23, an operation packet generator 24, a control part 25, an address latch 26, a packet latch 27, and a memory latch 28. Since the waiting memory consists of the two-port memory 21 where read and write of different addresses can be simultaneously executed, the write operation of a preceding waiting operation out of two continuous waiting operations and the read operation of the succeeding waiting operation are simultaneously executed, and waiting operations are executed in parallel by pipeline. Thus, the packet waiting processing speed is increased.

66. 发明专利

JPH02100767A DATA DRIVE TYPE DATA DISPLAY DEVICE 失效
公开(公告)号：JPH02100767A
公开(公告)日：1990-04-12
申请号：JP25430788
申请日：1988-10-07
申请人： SANYO ELECTRIC CO
发明人： MIURA HIROKI , TANAKA KAZUYUKI , SHIMIZU MASAHISA , MORI NORIAKI
IPC分类号： G09G5/06 , G06T1/00 , G09G5/00 , G09G5/36
摘要： PURPOSE:To realize the parallel arithmetic and drawing operations by detecting a specific data packet group among plural data packets based on the control information and using the detected packet group to actuate a drawing means or a drawing display control means. CONSTITUTION:When one of two data packets is inputted, a queuing memory means 9 checks whether the other data packet is queuing or not. If not, the means 9 waits for the arrival of the data on the packet of the other side. If the other packet is queuing, it is decided that both the address and data values are ready in terms of a drawing operation of a single picture element. Thus the writing processes are applied to the frame memories FM1-FM4 based on those data and address values. Thus it is possible to attain a prescribed drawing process regardless of the sequence where plural data or address value data packets reach a display device from a data drive type calculating device.

67. 发明专利

JPS6474615A DATA INPUT/OUTPUT CIRCUIT 失效
公开(公告)号：JPS6474615A
公开(公告)日：1989-03-20
申请号：JP23157687
申请日：1987-09-16
申请人： SANYO ELECTRIC CO
发明人： FUKUDA MITSUYOSHI , SHIMIZU MASAHISA , OHASHI HIDENORI , KAWAGUCHI MASAKI
IPC分类号： G06F5/00 , G06F7/76 , H03M9/00 , H04L13/10 , H04L29/06
摘要： PURPOSE:To transfer data different in format by switching the direction of a shift register in accordance with the direction of data transfer and switching an input gate circuit in accordance with an effective data length to select the input position of the register. CONSTITUTION:In case of a data format (a), a control circuit 20 sets a control signal U/D to 0 to control a reversible shift register 1 to the up-shift direction and sets a control signal OG1 to 1 to turn on only an output gate 8. 16-bit data sent in order from the MSB is successively shifted to registers 2 and 3 from a input SU1 of the reversible shift register 1 by a synchronizing signal Syncl and is taken into registers 2 and 3. This data is held in input latches 13 and 14 by a latch pulse LCK1 from the circuit 20 and is sent to a data bus 19. This data is held in output latches 16 and 17 by a latch pulse LCK2 and is preset to registers 2 and 3. Data is outputted as serial data SOUT through the gate 8 by applying 16 synchronizing signals Syncl.

68. 发明专利

JPS63280351A DATA STORAGE DEVICE 失效
公开(公告)号：JPS63280351A
公开(公告)日：1988-11-17
申请号：JP11620487
申请日：1987-05-13
申请人： SANYO ELECTRIC CO
发明人： TANAKA KAZUYUKI , MIURA HIROKI , SHIMIZU MASAHISA
IPC分类号： G06F12/00 , G06F9/44 , G06F15/82
摘要： PURPOSE:To efficiently store and refer to data sets by storing a data set having a set name, address information of its elements, and its address and holding the set name and write data and not only writing data in a prescribed position but also outputting a data packet in accordance with input of the data packet. CONSTITUTION:A data set, its address information, and its address are stored in a data memory 18, a pointer memory 12, and a pointer address memory 9 respectively, and the header and data of the input packet are held in registers 2 and 3 respectively. A processing indicating code 5 from the register 2 is decided by a decision control circuit 7 to output a control signal 8 of, for example, pointer setting, and the set name is loaded from the register 2 to a set name change means 27 to read out a memory 9. Data 6 is written in a memory 12 based on the address obtained from contents of the register 2, and a return code or the like of a memory 20 with contents of the means 27 as the address is latched in a register 21, and an acknowledge packet having its contents as the first word is outputted.

69. 发明专利

JPS63279339A DATA STORAGE DEVICE 失效
公开(公告)号：JPS63279339A
公开(公告)日：1988-11-16
申请号：JP11421887
申请日：1987-05-11
申请人： SANYO ELECTRIC CO
发明人： TANAKA KAZUYUKI , MIURA HIROKI , SHIMIZU MASAHISA
IPC分类号： G06F12/02 , G06F9/44 , G06F12/00 , G06F12/06 , G06F15/82
摘要： PURPOSE:To enable a data storage device to produce the new control information after a real address is produced and read out, by handling data between a data processor and a data recorder in the form of a group of plural data. CONSTITUTION:When data are read out, a data packet containing a group name is delivered to a data storage device. When a pointer address memory (pam) is referred to by the group name, a real address of a data element is produced by a chain of pointers set among memories. Then a data element is read out and at the same time the real address of a data element to be read next out of the same group is produced by a pointer replacement means (pc) and written into a pointer memory. This procedure is repeated by several times together wit the automatic replacement of group names. Thus the specific data elements on plural different data groups are continuously read out in response to the arrival of a single data packet.

70. 发明专利

JPS63261440A DATA STORAGE DEVICE 失效
公开(公告)号：JPS63261440A
公开(公告)日：1988-10-28
申请号：JP9645487
申请日：1987-04-20
申请人： SANYO ELECTRIC CO
发明人： TANAKA KAZUYUKI , MIURA HIROKI , SHIMIZU MASAHISA
IPC分类号： G06F12/00 , G06F9/44 , G06F15/82
摘要： PURPOSE:To reduce overhead for address setting by continuously accessing elements in a set by applying a set name in order to update a pointer to the address of an element to be successively accessed in the set. CONSTITUTION:A data packet loads the set name of a required data set to a counter. The contents of a pointer address memory (pam) are read out by using the output of the counter as its address and then latched to a register (r). The contents of a pointer memory (pm) and a differential memory (dim) are read out by using the contents of the register (r) as their addresses and latched to an address register (ar). Then, the contents of a data memory (dm) are accessed by using the contents of the address register (ar) as an address. The pointer and the difference are added to each other by a pointer updating means (pc) and the added value is written in the memory (pm). Consequently, overhead for setting up an address corresponding to the element can be reduced.

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