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61. 发明专利

JPS5836500B2 失效
公开(公告)号：JPS5836500B2
公开(公告)日：1983-08-09
申请号：JP6400474
申请日：1974-06-07
申请人： HITACHI LTD
发明人： OOTSUKA KANJI
IPC分类号： H05K1/02 , H01L23/12 , H01L23/36 , H05K1/00 , H05K5/00 , H05K7/20

62. 发明专利

JPS57154861A PACKAGE 失效
公开(公告)号：JPS57154861A
公开(公告)日：1982-09-24
申请号：JP3941681
申请日：1981-03-20
申请人： HITACHI LTD
发明人： OOTSUKA KANJI , USAMI TAMOTSU , SHIRAI MASAYUKI , SAWARA KUNIZOU , TAGAMI BUNICHI
IPC分类号： H01L23/12 , H01L23/52 , H01L23/64
摘要： PURPOSE:To reduce the number of layers for the subject package by a method wherein, in the case of a laminated package, intervals are provided so that the prescribed wiring impedance will be obtained, and a ground pattern is provided at the adjoining section of a signal line. CONSTITUTION:A signal wiring 2 is provided on the surface where the IC chip of the ceramic base 1 on the package will be installed, and the ground pattern 3 is provided adjacent to the wiring 2. Also, on the inner end section of the ground pattern 3, posts 2a and 3a are provided respectively for wire bonding, and pads 2b and 3b whereon a lead will be installed are provided on the outer end section. At this point, the interval d and the wiring width w of the ground pattern are determined using the diagram of impedance characteristics for w/ (w+2d), and this enables the wiring 2 to have a fixed impedance value for its wiring characteristics.

63. 发明专利

JPS56166392A PARTIAL PLATING JIG 失效
公开(公告)号：JPS56166392A
公开(公告)日：1981-12-21
申请号：JP7013880
申请日：1980-05-28
申请人： HITACHI LTD
发明人： MIYAMOTO MITSUO , SEKIHASHI MASAO , SUGITANI ISAO , OOTSUKA KANJI
IPC分类号： C25D5/02 , C25D5/56 , C25D17/06 , C25D17/08 , H05K3/24
摘要： PURPOSE:To subject only the required parts to partial plating surely, and effectively use a plating soln. by providing a rubber base for airtight sealing, a spring electrode, and a means for pressing the object to be plated to a plating base plate at the time of carrying out partial plating on electronic parts and the like. CONSTITUTION:A spring electrode 6 is mounted to a plating base plate 5 consisting of an electrode 4 taking electric current for plating from a power source and epoxy coating 15, and a rubber base 7 is provided on the base plate 5. A ceramic substrate 1 having a stud 2 and a plating part 3 are placed on the plate 7. A substrate hold- down 10 is mounted and fixed to the plate 5. Electric current is flowed to the stud 2 of the substrate 1 held down by the substrate hold-down 10 via the spring electrode 6 past the electrode 4, after which it is transferred to the plating part 3. At this time, the stud 2 is tightly sealed in the recess of the rubber base 7, and is perfectly sealed from the outside, thus only the plating part 3 on the top surface is plated, hence the wasteful use of the plating soln. is obviated.

64. 发明专利

JPS56104445A LEADLESS SEMICONDUCDOR DEVICE AND JUNCTION STRUCTURE FOR SUBSTRATE 失效
公开(公告)号：JPS56104445A
公开(公告)日：1981-08-20
申请号：JP685980
申请日：1980-01-25
申请人： HITACHI LTD
发明人： SAKAMOTO TATSUJI , HIOKI SUSUMU , OOTSUKA KANJI
IPC分类号： H01L21/60 , H01L21/58
摘要： PURPOSE:To prevent the thermal fatigue breakdown of the junction of the semiconductor due to thermal strain by increasing the interval between the substrate and the semiconductor in response to the diameter of a land when the substrate is connected in leadless manner and forming the configuration of the junction linearly or in a curved manner. CONSTITUTION:When a silicon element 1 is connected leadlessly to a ceramic substrate 2 with solder 3, the interval therebetween is increased in response to the diameters of the lands 6a, 6b to thus form the configuration of the solder at the connection linearly or in a curved manner. Thus, it can prevent the thermal fitigue breakdown of the junction due to the thermal strain caused by the thermal expansion difference therebetween.

65. 发明专利

JPS5685842A SEMICONDUCTOR DEVICE HAVING HEAT DISSIPATING FIN 失效
公开(公告)号：JPS5685842A
公开(公告)日：1981-07-13
申请号：JP16153479
申请日：1979-12-14
申请人： HITACHI LTD
发明人： OOTSUKA KANJI , SEKIHASHI MASAO , FURUKAWA MICHIAKI , IIDA SATOSHI
IPC分类号： H01L23/40 , H01L23/08 , H01L23/373
摘要： PURPOSE:To secure the reliability of the mounting portion of a semiconductor device having heat dissipating fins by soldering the stud of the heat dissipating fins through a hard metal thin layer having similar heat expansion coefficient to ceramic on a soft metal layer having high thermal conductivity on the outer wall of a semiconductor container. CONSTITUTION:A hard metal plate 3 of Mo or W is placed on a soft metal thin plate 2 of pure copper or pure silver having a preferable thermal conductivity to match a stress, and a stud 4 of copper or pure silver is soldered at 9a-9c with eutectic silver. Since the thermal stress between a brittle ceramic and the stud of different type material therefrom is alleviated and absorbed by the layers 2 and 3 when the stud 4 is mounted on a ceramic substrate 1 to which lead wires 15 are welded at 13 with this configuration, the ceramic substrate cannot be destroyed and the heat dissipating fins 5 having low cost, high performance and high reliability can be really mounted.

66. 发明专利

JPS5649550A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5649550A
公开(公告)日：1981-05-06
申请号：JP12413179
申请日：1979-09-28
申请人： HITACHI LTD
发明人： OOTSUKA KANJI , SEKIHASHI MASAO , USAMI TAMOTSU
IPC分类号： H01L23/34 , H01L23/057 , H01L23/12
摘要： PURPOSE:To prevent the destruction of semiconductor devices by using kovan or 42% Ni-Fe alloy for fastening to a ceramic container a device fitting body made of Mo or W so that the relative distortion of the container and device fitting body due to heating may be reduced. CONSTITUTION:A bridge ring 2 of Kover of 42% Ni-Fe alloy is adhered, using a solder 8, to a metallized layer 13 located at the bottom of the central square-window part of a container-shaped ceramic body 10 mainly consisting of alumina or beryllia on which the metallized layers 11-14 of wire bonding, fastening, bridging and pin-fitting electrodes are provided. A heat radiating stud 1 and a device fitting plate 3 made of Mo or W are fastened to the lower and upper sides respectively of the layer 13 surrounded by the ring 2 and exposed. A semiconductor device 4 is fitted on the plate 3 and a given pattern of wiring is made using wire 5. Thereafter, the upper surface of the device 4 is covered with a Kovar or 42% Ni-Fe alloy cover 6 using a solder 9.

67. 发明专利

JPS55156339A FORMING METHOD OF BUMP ELECTRODE 失效
公开(公告)号：JPS55156339A
公开(公告)日：1980-12-05
申请号：JP6389779
申请日：1979-05-25
申请人： HITACHI LTD
发明人： KAWANOBE TOORU , MIYAMOTO KEIJI , OOTSUKA KANJI
IPC分类号： H01L21/60 , H01L21/92
摘要： PURPOSE:To obtain a bump electrode with reduced size and high density by a method wherein solder plating process for forming a solder electrode on a semiconductor substrate is divided into two steps and the applied solder layer is swollen to a shape of a semisphere under the action of surface tension by melting it after each plating. CONSTITUTION:An SiO2 film 17 is coated on the surface of an Si substrate 1, a passivation film 16 is provided on its periphery and then a metal film 8 is coated thereon overall. On this metal film 8, polyimide resin 11 is covered except for the region where a solder bump electrode is to be provided, and the first solder layer 12 is formed on the exposed portion of the film 8 by using the film 8 as a plating electrode. Then, the first solder layer 12 is swollen to a shape of a semisphere by wet-backing so as to form the first solder bump electrode 13. To compensate the less height of this electrode 13, plating process is repeated again to form the second solder layer 14 on the electrode 13, and thereafter the second solder bump electrode 15 with increased height is obtained under the action of surface tension by melting the electrode 13 and the layer 14. In such a manner, the solder electrode increases its height under action of the surface tension by melting it after coating the solder as a thin layer, thereby reducing the coating surface area and increasing the density thereof.

68. 发明专利

JPS55143040A TAPE CARRIER TYPE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS55143040A
公开(公告)日：1980-11-08
申请号：JP5029679
申请日：1979-04-25
申请人： HITACHI LTD
发明人： OOTSUKA KANJI , OONISHI SHINJI , KAWAMOTO HIROSHI
IPC分类号： H01L21/60 , H01L23/556
摘要： PURPOSE:To stabilize operation, by coating an alpha-ray shielding resin layer on an active region which is provided in a semiconductor chip and which is likely to perform wrong action when alpha-rays are irradiated upon the region. CONSTITUTION:Bump electrodes 11 are attached to the surface of a semiconductor IC chip 10 near its edges. The chip 10 has an active region such as a memory cell on the surface. Cu leads 12 are connected to the bump electrodes 11 so that the leads project outward. An alpha-ray shielding layer 13 of polyimide resin, polyester resin or the like with a thickness of 25-60mum is fixed on the leads 12 opposite the bump electrodes 11 so that the memory cell region of the chip 10 exposed between the electrodes is covered with the resin layer. As a result, no pairs of electron and positive hole are produced due to the radiation of U or Th contained in a package and troubles such as the fall or inversion of the logical level of stored information do not occur even if a device is made of the tape carrier type.

69. 发明专利

JPS55113351A INTEGRATED CIRCUIT MODULE 失效
公开(公告)号：JPS55113351A
公开(公告)日：1980-09-01
申请号：JP1979979
申请日：1979-02-23
申请人： HITACHI LTD
发明人： OOTSUKA KANJI , SEKIHASHI MASAO , USAMI TAMOTSU , HOSOSAKA SATORU , MIZUNO AKIRA , YASUDA TOMIROU , SOGA TASAO , ISHIDA MASAKATSU
IPC分类号： H01L23/32 , H01L21/50 , H01L23/34 , H01L23/40 , H01L23/52
摘要： PURPOSE:To increase assembly density and heat discharge effect by a structure wherein a plurality of IC chips are bonded on a wiring substrate by using flexible leads and a heat discharge body is fitted on the chip surface. CONSTITUTION:A plurality of IC chips 1 including bipolar LSI for high speed logic use are fixed on multi-layered wiring substrate 1 made of alumina ceramic and provided with a plurality of terminal pins 6 projecting on its back surface, by means of flexible leads 5. Next, heatsink 3 having heat discharge fin 3A is fixed on the whole body of these chips, and its end is connected to the end of substrate 1 by means of bolt 7. When an IC module is constructed in this way, good heat discharge effect is obtained, and even if thermal stress is produced due to the difference of thermal expansion coefficients, no crack occurs in the chips.

70. 发明专利

JPS5559794A CIRCUIT BOARD 失效
公开(公告)号：JPS5559794A
公开(公告)日：1980-05-06
申请号：JP13162778
申请日：1978-10-27
申请人： HITACHI LTD
发明人： OOTSUKA KANJI , USAMI TAMOTSU , SEKIHASHI MASAO , FURUKAWA MICHIAKI , ISHIDA MASAKATSU , KOBAYASHI FUMIYUKI , OOKI NOBUAKI
IPC分类号： H05K1/11 , H05K3/46

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