专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明专利

JPS5844560A DATA TRANSFER CONTROLLING SYSTEM FOR PARALLEL PROCESSOR SYSTEM 失效
公开(公告)号：JPS5844560A
公开(公告)日：1983-03-15
申请号：JP14097681
申请日：1981-09-09
申请人： HITACHI LTD
发明人： YABUUCHI SHIGERU , ENDOU TAKESHI , KODAMA KAZUYUKI , IDE TOSHIYUKI
IPC分类号： G06F15/16 , G06F9/52 , G06F15/177 , G06F15/80
摘要： PURPOSE:To attain a high-speed arithmetic process for a parallel processor system, by having a control so that just a single processor is set under the transmission mode with other pricessors all set under the reception mode. CONSTITUTION:A control arithmetic controller 102 monopolizes a common bus 101 to transfer the data among processors after the arithmetic execution phase and at the same time sets the processors 103-106 under the reception mode by the monopolizing signal. Then a switch control signal is fed to the processor 103 via a signal line 107 for the switching to the transmission mode. Thus the processor 103 is set under the transmission mode. The processor 103 feeds the data of a number indicated previously to the processors and then switches its own working mode into the reception mode. Then the control signal is fed to the processor 104 via a signal line 108 in order to set the processor 103 under the transmission mode. In such way, the transfer of data is carried out among n-units of processors, and the processor 102 is switched to the arithmetic execution phase when the switch signal to the transmission mode arrives at the processor 102.

62. 发明专利

JPS57212492A COLOR DIVIATION CORRECTOR FOR COLOR BRAUN TUBE 失效
公开(公告)号：JPS57212492A
公开(公告)日：1982-12-27
申请号：JP9898881
申请日：1981-06-24
申请人： HITACHI LTD
发明人： KAMATA YASUHARU , KUWABARA HIROSHI , IDE TOSHIYUKI , YAMASHITA KENKICHI , TAKAHASHI KOUJI
IPC分类号： H01J29/54 , G09G1/00 , G09G1/04 , G09G1/28 , H04N9/28 , H04N17/04

63. 发明专利

JPS5786180A MEMORY DEVICE HAVING ADDRESS CONVERTING MECHANISM 失效
公开(公告)号：JPS5786180A
公开(公告)日：1982-05-29
申请号：JP16075880
申请日：1980-11-17
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： FUKUNAGA YASUSHI , BANDOU TADAAKI , MATSUMOTO HIDEKAZU , HIRAOKA YOSHINARI , IDE TOSHIYUKI , KATOU TAKESHI , KAWAKAMI TETSUYA
IPC分类号： G06F12/08 , G06F12/10 , G06F15/16 , G06F15/177
摘要： PURPOSE:To manage with only one virtual address converting mechanism in a system, by providing a memory control part with an address converting mechanism which converts an accessed virtual address into the actual address of a memory part. CONSTITUTION:Memory requests from a processor are all supplied as virtual addresses on a common bus 11 and set in a virtual address register 21; and a conversion table 30 is stored in a memory part 16, and a high-speed buffer (TLB) 22 wherein accessed address information is stored is provided at a control part. The V bit 61 and C bit 62 of the TLB22 indicate the current states of corresponding pages, and when the V bit 61 is a 0, it is shown that the contents of the corresponding page of the TLB22 are insignificant data; when a 1, 1, the paging of the page is in process and when a 1, 0, the page is stored in the memory part 16, showing memory access is possible. When the 1, 1, only access from a file control processor is permitted.

64. 发明专利

JPS5783948A Information processing system 失效
标题翻译：信息处理系统
公开(公告)号：JPS5783948A
公开(公告)日：1982-05-26
申请号：JP15953580
申请日：1980-11-14
申请人： Hitachi Ltd
发明人： YASUMOTO SEIICHI , IDE TOSHIYUKI , FUSHIMI HITOSHI , OKADA MASAKAZU , MIZOKAWA SADAO
IPC分类号： H04L29/14 , G06F11/00 , G06F13/00
CPC分类号： G06F11/00
摘要： PURPOSE:To detect a device fault in its early stage and to isolate a fault position by sectioning an information processing system by hierarchies and by checking the function of each hierarchy. CONSTITUTION:In an information transfer system extending from a highest-priority main storage device 2 to a lowest-priority input-output equipment 10, a part including halfway repeaters (5, 8 and 9) is divided into hierachies as minimum sections, and the functions of each section are checked. First, when the functions of the hierachy 30 of a monitoring processor 3 and an input-output control processor 5 are checked, the monitoring processor 3 sends a start command I, which indicates the details of a diagnosis, a transfer parameter of known data, etc., to the input-output control processor 5. On receiving the start command I, this processor 5 decodes the parameter to receive written data for the diagnosis in the data area of the monitoring processor 3 by DMA transfer, and then returns the said written data to the monitoring processor 3 as readout data. After the said operation ends, the monitoring processor is informed of that and the next hierarchy check is started.
摘要翻译：目的：通过分层次检查信息处理系统，并通过检查每个层次结构的功能来检测早期的设备故障并隔离故障位置。构成：在从最高优先级的主存储装置2延伸到最低优先级的输入输出装置10的信息传送系统中，包括中途中继器（5,8,9）的部分被划分成最小部分，检查每个部分的功能。首先，当监视处理器3和输入输出控制处理器5的等级30的功能被检查时，监视处理器3发送指示诊断的细节的开始命令I，已知数据的传送参数，在接收到开始命令I的情况下，该处理器5对该参数进行解码，以通过DMA传送在监视处理器3的数据区域中接收用于诊断的写入数据，然后返回所述将写入的数据作为读出数据发送到监视处理器3。在所述操作结束之后，通知监视处理器，并开始下一个层次结构检查。

65. 发明专利

JPS54109339A SHARED INPUTTOUTPUT BUS CONTROLLER 失效
公开(公告)号：JPS54109339A
公开(公告)日：1979-08-27
申请号：JP1544778
申请日：1978-02-15
申请人： HITACHI LTD
发明人： MORIOKA TAKAYUKI , KATOU TAKESHI , IDE TOSHIYUKI
IPC分类号： G06F15/16 , G06F3/00 , G06F12/06 , G06F13/00 , G06F15/177
摘要： PURPOSE:To make it possible to extend memory addresses without changing input- output devices by providing a method, which is stored temporarily with bank numbers corresponding to input-output devices, into a shared input-output bus controller. CONSTITUTION:Processor 1 consists of exclusive-use bus controller 13, memory unit 12 and common-use input-output bus 7, and channel controller 9D' has direct- memory-access-DMA transfer address register 14. Common-use input-output bus controllers 5 and 13 are equipped with bank registers 15 and 16. Now, when card reader 10 performs DMA transfer, bank numbers are written into corresponding parts of registers 15 and 16 and addresses are stored in register 14. Once the DMA transfer starts, the bank number equivalent to reader 10 inside of register 16 is transmitted to unit 1. At this time, unit 5 transmits a suppression signal 18 to unit 13 in order to prevent the transmission of the bank number from register 15. When the DMA device is connected to bus 3, the bank number is sent out from register 15.

66. 发明专利

JPS5456150A COMMON BUS PROTECTION 失效
公开(公告)号：JPS5456150A
公开(公告)日：1979-05-04
申请号：JP12145577
申请日：1977-10-12
申请人： HITACHI LTD
发明人： MORIOKA TAKAYUKI , IDE TOSHIYUKI
IPC分类号： H02H7/00 , G06F13/00 , H02H7/22
摘要： PURPOSE:To obtain an immediate operation with a simple mechanism by applying specific current or voltage to its faulty location at fault and automatically separating the faulty input and output device which is connected to a common bus using its current or voltage. CONSTITUTION:When either of transmission gates 6 becomes faulty owing to some causes, such as regular continuity, the fault is detected by a detection circuit 20. As a result, a switch 12 closes and current is applied to a common bus 1 from a power supply 14 through this switch 12 and a diode 13. This permits current to be applied to a current cut-off element 11 connected to the output section of the faulty transmission gate 6 and this element 11 to blow off. This also permits the faulty transmittion gate 6 to be separated from the common bus 1.

67. 发明专利

JPS53109446A CARRYING ABOUT SYSTEM FOR CONTROL STATION 失效
公开(公告)号：JPS53109446A
公开(公告)日：1978-09-25
申请号：JP2379677
申请日：1977-03-07
申请人： HITACHI LTD
发明人： NAKANO TAKESHI , FUSHIMI HITOSHI , IDE TOSHIYUKI
IPC分类号： G06F13/00 , G06F3/00 , G06F13/36
摘要： PURPOSE:To efficiently and surely select the first CST and its shunt ST from the station ST having a number of control station CST functions, by only providing a simple switch for setting.

68. 发明专利

JPS5389603A LOOPPTYPE DATA TRANSMISSION SYSTEM 失效
公开(公告)号：JPS5389603A
公开(公告)日：1978-08-07
申请号：JP391477
申请日：1977-01-19
申请人： HITACHI LTD
发明人： OKADA MASAKAZU , IDE TOSHIYUKI
IPC分类号： G06F13/00 , H04L12/42
摘要： PURPOSE:To make the circuit small-size and low-price and improve the reliability of system by disusing the conventional third frequency signal by using the specific bit signal as the circuit release signal.

69. 发明专利

JPS5372430A CONTROL SYSTEM FOR COMMON USE INPUT AND OUTPUT BUS 失效
公开(公告)号：JPS5372430A
公开(公告)日：1978-06-27
申请号：JP14774676
申请日：1976-12-10
申请人： HITACHI LTD
发明人： TOMITA NOBUO , IDE TOSHIYUKI
IPC分类号： G06F13/36 , G06F3/00
摘要： PURPOSE:To enable the quick common use I/O changeover control, by processing the coupling section between the buses consisting of the linkage bus and the window switch in the same manner as convetional I/O units.

70. 发明专利

JPS5336104A TROUBLE DISCRIMINATION EQUIPMENT IN LOOPPTYPE DATA TRANSMISSION SYSTEM 失效
公开(公告)号：JPS5336104A
公开(公告)日：1978-04-04
申请号：JP10993376
申请日：1976-09-16
申请人： HITACHI LTD
发明人： OKADA MASAKAZU , IDE TOSHIYUKI , FUSHIMI HITOSHI , YASUMOTO SEIICHI
IPC分类号： H04L25/02 , G06F13/00 , H04B17/40 , H04L12/437
摘要： PURPOSE:When a trouble occurs in a circuit, respective stations perform particular operations to inform the system of the trouble, thereby making it possible to realize the localization of the trouble easily.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式