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61. 发明专利

JP2000091535A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2000091535A
公开(公告)日：2000-03-31
申请号：JP25893698
申请日：1998-09-11
申请人： HITACHI LTD
发明人： HASHIMOTO KOJI , KURODA KENICHI , YADORI SHOJI
IPC分类号： H01L21/768 , H01L21/822 , H01L21/8234 , H01L21/8239 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To make compatible the contact hole formation process (gate-SAC) of a DRAM and the contact hole formation process (L-SAC) of a logic LSI compatible in the manufacture of a semiconductor integrated circuit device having a DRAM and a logic LSI together. SOLUTION: A silicon nitride film 9 is left only at the upper part of region for forming the gate electrode 8A (a word line WL) of MISFET for the memory cell selection of a DRAM, and the silicon nitride film 9 is not left at the upper part of the gate electrode 8B of a MISFET for constituting the logic LSI and the upper part of the gate electrodes 8C and 8D for constituting the memory cell of an SRAM. Thereafter, by etching using the silicon nitride film 9 and a photoresist film 10 for a mask, the gate electrode 8A (word line WL) and the gate electrodes 8B-8D are pattern formed at the same time.

62. 发明专利

JPH11134077A PROCESSOR AND SYSTEM FOR DATA PROCESSING 失效
公开(公告)号：JPH11134077A
公开(公告)日：1999-05-21
申请号：JP29804297
申请日：1997-10-30
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： YOSHIOKA SHINICHI , SHIBA JUNICHI , KAWASAKI IKUYA , MATSUDA KENGO , HASHIMOTO KOJI
IPC分类号： G06F1/32 , G06F1/04 , G06F12/08
摘要： PROBLEM TO BE SOLVED: To provide a data processor which properly control the power consumption state of an built-in module according to whether or not dynamically changed operation is necessary. SOLUTION: Hit information(HIT) indicating a cache miss of a cache memory (4) is referred to and only when a bus controller (7) and an external interface circuit (90) need to be placed in operation, clock signals (ICLK, BCLK, and PCLK) are supplied to those circuits, but in a state of a cache hit where no external access is needed, the supply of the clock signals to the bus controller, external interface circuit, etc., is stopped. Consequently, the power consumption states of the bus controller, input/output circuit, etc., can properly be controlled according to whether or not operation dynamically changed according to the state of the cache memory is necessary and the power consumption of the data processor with the built-in cache memory can be reduced.

63. 发明专利

JPH1167930A SEMICONDUCTOR INTEGRATED DEVICE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JPH1167930A
公开(公告)日：1999-03-09
申请号：JP21757797
申请日：1997-08-12
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： HOSHINO YUTAKA , FUKUDA KAZUJI , KOIDE MASAKI , HASHIMOTO KOJI , YOSHIDA YASUKO , TOBA KOICHI , IKEDA SHUJI , HAGA SATORU
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/8244 , H01L27/092 , H01L27/11 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To increase the ratio of a memory cell and also to improve the drive capacity of peripheral circuit in a semiconductor integrated circuit device having a SRAM(static random access memory). SOLUTION: In order to form a low concentration semiconductor region in the source-drain region of a memory cell transfer MISFET Qt1 and an n- channel MISFET in a peripheral circuit, a manufacturing method consists of two steps. A first step of ion implanting both low impurity concentration semiconductor regions with n-type impurities and a second step of ion implanting the low impurity concentration semiconductor region in the n-channel MISFET of a peripheral circuit, only with the n-type impurities.

64. 发明专利

JPH10200101A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH10200101A
公开(公告)日：1998-07-31
申请号：JP138797
申请日：1997-01-08
申请人： HITACHI LTD
发明人： MINAMI MASATAKA , HASHIMOTO KOJI , UENISHI TOSHIYA
IPC分类号： H01L21/316 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To minize scraped amount of a field oxide film and effectively remove a white ribbon by forming a sacrifice oxide film twice and then removing. SOLUTION: With a thermal oxidation process, the first sacrifice oxide film 7 is formed on the surface of the element formation region of a p-type semiconductor substrate 1. In the process, the surface of a white ribbon 6 is also oxidized. Then the first sacrifice oxide film 7 is removed, while such part of the white ribbon 6 as oxidized is also removed. In addition, a field oxide film 5 is etched by such an amount as to remove the sacrifice oxide film 7. Then, while the second sacrifice oxide film 8 is formed in a similar process, the white ribbon 6 is also oxidized. Then, the second sacrifice oxide film 8 is removed, thus the white ribbon 6 is entirely removed. The field oxide film 5 is etched by such an amount as the second sacrifice oxide film 8 is removed. With no white ribbon 6 present, a gate oxide film 9 of even film thickness is formed in the following process.

65. 发明专利

JPH10170690A METHOD TO IRRADIATE IRRADIATED OBJECT IN PRESSURE PIPE TYPE NUCLEAR REACTOR FOR SHORT PERIOD 失效
公开(公告)号：JPH10170690A
公开(公告)日：1998-06-26
申请号：JP32955696
申请日：1996-12-10
申请人： HITACHI LTD
发明人： HASHIMOTO KOJI , SATOU SHINICHIROU , NAKAMURA FUMITO
IPC分类号： G21C23/00
摘要： PROBLEM TO BE SOLVED: To isolate a cylinder body housing an irradiated object and a moderator from each other, and take in and out the irradiating object when a nuclear reactor is operated by arranging the cylinder body to constitute a moderator boundary in an existing pipe opened in the moderator. SOLUTION: A cylinder 17 such as aluminium having the small neutron absorbing cross-sectional area capable of containing an irradiated object 16, is arranged in contact on an inside surface of a control rod guide pipe 13 so as to fulfill a function of a moderator boundary. In the cyclinder 17, a space up to a control rod driving device existent part from a lower part of a calandria tank 1 is used as an installing range, and the upper end of the cylinder 17 is expanded in a collar shape, and is fixed by a bolt 30 by sandwiching a seal member 29 between it and a control rod holding flange 28. A wire 31 and the irradiating object 16 in the cylinder 17 are connected to each other by remote control of a control rod replacing device 6, and a wire winding drum 18 is rotated by driving a motor 27 from outside of a housing vessel, and the irradiated object 16 is wound up by the wire 31, and is moved by remote control to the control rod guide pipe 13 from which a control rod is removed or a rack position in a fuel replacing pool.

66. 发明专利

JPH06268177A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH06268177A
公开(公告)日：1994-09-22
申请号：JP4911793
申请日：1993-03-10
申请人： HITACHI LTD
发明人： ISHIDA MOTOKO , OKUYAMA KOSUKE , IKEDA SHUJI , KANAI FUMIYUKI , HASHIBA SOICHIRO , HASHIMOTO KOJI , YOSHIZAKI KAZUO
IPC分类号： H01L21/318 , H01L21/336 , H01L21/8238 , H01L21/8244 , H01L27/092 , H01L27/11 , H01L29/78 , H01L29/786 , H01L29/784
摘要： PURPOSE:To improve mutual conductance (Gm) of a loading MISFET constituted of a polycrystalline silicon film in a fully CMOS type SRAM and to prevent deterioration of characteristics caused by entering of water. CONSTITUTION:In an SRAM wherein memory cell is constituted of transfer MISFETQt1, Qt2 formed on a main surface of a semiconductor substrate 1 and a flip flop circuit consisting of driving MISFETQd1, Qd1 formed on a main surface of the semiconductor substrate 1 and loading MISFETQp1, Qp2 formed of a polycrystalline silicon film deposited in an upper part of the driving MISFETQd1, Qd2, a silicon nitride film 28 which is so thick as to make it easy to transmit hydrogen and hard to transmit water is provided to an upper part of the loading MISFETQp1, Qp2.

67. 发明专利

JPH0595113A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH0595113A
公开(公告)日：1993-04-16
申请号：JP25347191
申请日：1991-10-01
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SHIMIZU AKIHIRO , YAMANAKA TOSHIAKI , HASHIMOTO NAOTAKA , HASHIMOTO KOJI , OOKI NAGATOSHI , ISHIDA HIROSHI
IPC分类号： H01L29/78
摘要： PURPOSE:To provide a MIS-type field effect transistor having high reliability and high current driving ability and is proper for high integration. CONSTITUTION:A source and a drain have an LDD structure, a sidewall spacer 6 is provided to an area near the sidewall of a gate electrode above a low concentration diffusion layer 2 thereof, a gate electrode bottom part protrudes and a gate electrode protruding part is buried inside a semiconductor substrate 1 in a self-alignment manner. Thereby, it is possible to bury an overlapping part of the low concentration diffusion layer 2 and a gate electrode 5 inside the silicon substrate 1 in a self-alignment manner and to realize a semiconductor device having high reliability and high current driving ability through the plane occupied area of a transistor is small. Furthermore, contact between the transistor and an upper wiring layer can be formed in a self-alignment manner and a plane occupied area of the transistor can be further reduced.

68. 发明专利

JPH04320036A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH04320036A
公开(公告)日：1992-11-10
申请号：JP8654791
申请日：1991-04-18
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SHIMIZU AKIHIRO , YAMANAKA TOSHIAKI , JINRIKI HIROSHI , NAKADA MASAYUKI , HASHIMOTO NAOTAKA , HASHIMOTO KOJI
IPC分类号： H01L21/314 , H01L21/336 , H01L21/8242 , H01L21/8244 , H01L27/10 , H01L27/108 , H01L27/11 , H01L29/78 , H01L29/786
摘要： PURPOSE:To provide a semiconductor device having MISFETs suitable for high reliability and high current driving capacity. CONSTITUTION:A source/drain has an LDD structure provided with a high- dielectric side wall spacer 6 in a vicinity of the gate electrode side wall on top of a low-doped diffusion layer 2, and with another tunneling thin film insulating film 7 between the side wall spacer and the diffusion layer 2. A gate fringe field effect to the diffusion layer 2 is improved, and hot carrier deterioration special to the LDD structure is made hard to occur; therefore, improvement in reliability of field relaxation and improvement in current driving power can be realized simultaneously.

69. 发明专利

JPH04162473A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH04162473A
公开(公告)日：1992-06-05
申请号：JP28424190
申请日：1990-10-24
申请人： HITACHI LTD
发明人： UEDA KIYOTSUGU , SASAKI KATSURO , ISHIBASHI KOICHIRO , YAMANAKA TOSHIAKI , HASHIMOTO KOJI
IPC分类号： H01L27/11 , H01L21/8244
摘要： PURPOSE:To obtain a memory cell having a high software error resistance without increasing memory cell area by forming a load and drive transistor with single crystal semiconductor layer or polycrystalline semiconductor layer of two or more layers and predetermining a resistance value of one or both gate electrodes of a couple of drive transistors and load transistors. CONSTITUTION:A transfer transistor is formed within a P-type well 15 provided within an N-type substrate 37 with N-type high concentration impurity regions 5a, 5b (drain electrode, source electrode) and a first layer polysilicon film 6 (gate electrode). Moreover, a gate electrode 14b is formed by a second layer polysilicon film on an oxide film 11 provided on a gate electrode 4b (first layer polysilicon layer) of a drive MOS transistor. A load transistor consisting of polysilicon layer is formed by providing drain electrode 8, source electrode 18 and channel part 17 with a third layer polysilicon film. In this case, a resistance value of the gate electrode 14b is set to 10KOMEGA or more by not executing or executing a small amount of ion implantation to a part or to the entire part of the gate electrode 14b of the load transistor.

70. 发明专利

JPH03218667A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH03218667A
公开(公告)日：1991-09-26
申请号：JP28705990
申请日：1990-10-26
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ISHIBASHI KOICHIRO , SASAKI KATSURO , SHIMOHIGASHI KATSUHIRO , YAMANAKA TOSHIAKI , HASHIMOTO NAOTAKA , HASHIMOTO KOJI , SHIMIZU AKIHIRO
IPC分类号： G11C11/412 , G11C11/419 , H01L21/8244 , H01L27/11
摘要： PURPOSE:To decrease a memory cell in area and electric power consumption by a method wherein two drive MOSFETs and two transfer MOSFETs are specified in length and width of channel, and the current of an active load FET is set 1X10 A or above in intensity. CONSTITUTION:N channel drive MOSFETs 3 and 4 are set to be WDEFF and LDEFF respectively in effective length and width of channels, and N channel transfer MOSFETs 5 and 6 are set WTEFF and LTEFF respectively in effective length and width of channels. The memory cell ratio (WDEFF/LDEFF)/WTEFF/LTEFF is set smaller than 3. That is, when data is read out from a cell, as polysilicon TFTs 1 and 2 functioning as active loads through which an ON-current larger than 1X10 can be made to flow are used as memory cells, the memory cell ratio can be made smaller than 3 and the effective channel length WDEFF can be made small. By this setup, a memory cell be made small in occupying area.

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