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51. 发明专利

JP2008533723A Flat growth technology of semi-polar gallium nitride 有权
公开(公告)号：JP2008533723A
公开(公告)日：2008-08-21
申请号：JP2008500965
申请日：2006-03-10
申请人：ザリージェンツオブザユニバーシティオブカリフォルニアThe Regents of The University of California , 独立行政法人科学技術振興機構
发明人：ジェームス・エス・スペック , スティーブン・ピー・デンバース , トロイ・ジェー・ベーカー , ベンジャミン・エー・ハスケル , ポール・ティー・フィニ , 修二中村
IPC分类号： H01L21/205 , H01L33/00
CPC分类号： C30B29/406 , C30B25/02 , C30B25/18 , H01L21/0242 , H01L21/02433 , H01L21/0254 , H01L21/02658 , H01L33/007 , Y10S438/938
摘要：平坦な半極性窒化物薄膜の大面積が基板の表面に平行であるような、ミスカットスピネル基板上への平坦な半極性窒化物薄膜の成長方法。平坦な薄膜と基板は（１）特定の方向にミスカットした｛１００｝スピネル基板上に成長した｛１０−１１｝窒化ガリウム (ＧａＮ）、（２）｛１１０｝スピネル基板上に成長した｛１０−１３｝窒化ガリウム (ＧａＮ）、（３）｛１−１００｝サファイヤ基板上に成長した｛１１−２２｝窒化ガリウム (ＧａＮ）、および（４）｛１−１００｝サファイヤ基板上に成長した｛１０−１３｝窒化ガリウム (ＧａＮ）である。
【選択図】図２

52. 发明专利

JP2008192989A Semiconductor device and manufacturing method therefor 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008192989A
公开(公告)日：2008-08-21
申请号：JP2007028345
申请日：2007-02-07
申请人： Fujitsu Ltd , 富士通株式会社
发明人： FUKUDA MASAHIRO , SHIMAMUNE YOSUKE
IPC分类号： H01L29/78 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092
CPC分类号： H01L21/823814 , H01L21/02381 , H01L21/02447 , H01L21/0245 , H01L21/02502 , H01L21/02529 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/823807 , H01L29/165 , H01L29/66636 , H01L29/7848 , Y10S438/933 , Y10S438/938
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device, along with its manufacturing method, comprising an MOS transistor structure capable of efficiently applying stresses to a channel.
SOLUTION: The manufacturing method of the semiconductor device includes a process (a) where a gate insulating film 3 and a gate electrode 4 are formed on an Si surface of a semiconductor substrate; a process (b) where an insulating side wall spacer SW is formed on an insulating gate electrode sidewall; a process (c) where a recess 11 is formed in an Si region on both sides of the insulating sidewall spacer SW; a process (d) where a first SiGe layer 12a of critical film thickness or less is epitaxially grown on the semiconductor substrate surface that has been recessed; a process (e) where a second SiGe layer 12b of critical film thickness or less whose Ge composition is lower than the first SiGe layer 12a is epitaxial-grown on the first SiGe layer 12a; and a process (f) where a third SiGe layer 12a of critical film thickness or less whose Ge composition is higher than the second SiGe layer 12b is epitaxially grown on the second SiGe layer 12b.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件及其制造方法，其包括能够有效地向沟道施加应力的MOS晶体管结构。解决方案：半导体器件的制造方法包括其中在半导体衬底的Si表面上形成栅极绝缘膜3和栅极电极4的工艺（a）绝缘侧壁隔离物SW形成在绝缘栅电极侧壁上的工序（b）在绝缘侧壁间隔物SW的两侧的Si区域形成有凹部11的工序（c）其中在凹陷的半导体衬底表面上外延生长临界膜厚度或更小的第一SiGe层12a的工艺（d）其中Ge组分低于第一SiGe层12a的临界膜厚度或更小的第二SiGe层12b在第一SiGe层12a上外延生长的工艺（e）; 和其中Ge组分高于第二SiGe层12b的临界膜厚度或更小的第三SiGe层12a在第二SiGe层12b上外延生长的工艺（f）。版权所有（C）2008，JPO＆INPIT

53. 发明专利

JP2008103607A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008103607A
公开(公告)日：2008-05-01
申请号：JP2006286203
申请日：2006-10-20
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： TAMURA NOBUMASA , SUZUKI TAKESHI , OTANI KAZUHIRO
IPC分类号： H01L29/78 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/823807 , H01L29/7843 , Y10S438/938
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which a stress insulating film is formed on a gate electrode, preventing the reduction of a driving capability of an MIS transistor. SOLUTION: The semiconductor device has a first MIS transistor formed in a first active region 100b on a semiconductor substrate 100. The first MIS transistor comprises: a first gate insulating film 103b formed on the first active region 100b; a first gate electrode 104b formed on the first gate insulating film 103b; a first stress insulating film 111b which is formed on an upper face in the first gate electrode 104b and on a side face in a gate length direction for applying first stress to a channel of the first MIS transistor in the gate length direction; and a first underlaying insulating film 112 formed on a side face in a gate width direction in the first gate electrode 104b. The first stress insulating film 111b is not formed on the side face in the gate width direction of the first gate electrode 104b. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供在栅电极上形成应力绝缘膜的半导体器件，防止了MIS晶体管的驱动能力的降低。解决方案：半导体器件具有形成在半导体衬底100上的第一有源区100b中的第一MIS晶体管。第一MIS晶体管包括：形成在第一有源区100b上的第一栅极绝缘膜103b; 形成在第一栅极绝缘膜103b上的第一栅电极104b; 第一应力绝缘膜111b，其形成在第一栅电极104b的上表面和栅极长度方向的侧面上，用于向栅极长度方向的第一MIS晶体管的沟道施加第一应力; 以及形成在第一栅电极104b中的栅极宽度方向的侧面上的第一底层绝缘膜112。第一应力绝缘膜111b不形成在第一栅电极104b的栅宽度方向的侧面上。版权所有（C）2008，JPO＆INPIT

55. 发明专利

JP2006191004A Memory element and its manufacturing method 有权
标题翻译：记忆元素及其制造方法
公开(公告)号：JP2006191004A
公开(公告)日：2006-07-20
申请号：JP2005352408
申请日：2005-12-06
申请人： Dongbuanam Semiconductor Inc , ドンブアナムセミコンダクターインコーポレイテッド
发明人： KIM HEUNG JIN
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/78 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/0847 , H01L29/1054 , H01L29/66575 , Y10S438/938
摘要： PROBLEM TO BE SOLVED: To provide a split gate flash EEPROM by composing a control gate and a floating gate in a vertical position, and by downsizing a cell to realize a high coupling ratio and to decrease a programming voltage with its demagnetizing property improved with a part of the control and floating gate overlapped, and to provide its manufacturing method. SOLUTION: The split gate flash EEPROM comprises a semiconductor substrate having a trench, a tunneling oxide film formed on the both-side walls of the trench; the floating gate, a dielectric film, and the control gate independently and sequentially formed on the both-side walls on the trench on the tunneling oxide film; a buffer dielectric film formed on the floating gate, the dielectric film, and on the control gate side wall; a source junction formed on the trench bottom semiconductor substrate, a source electrode electrically connected to the source junction and formed in the trench between the buffer dielectric films; and a drain junction formed on the surface of the semiconductor substrate except the trench. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过在垂直位置构成控制栅极和浮动栅极来提供分离栅极快速EEPROM，并且通过使单元小型化以实现高耦合比并且以其退磁特性降低编程电压改进了一部分控制和浮动门重叠，并提供其制造方法。解决方案：分离栅极快速EEPROM包括具有沟槽的半导体衬底，形成在沟槽的两侧壁上的隧道氧化膜; 独立且顺序地形成在隧道氧化膜上的沟槽上的两侧壁上的浮栅，电介质膜和控制栅; 形成在浮动栅极，电介质膜和控制栅极侧壁上的缓冲电介质膜; 源极结，其形成在沟槽底部半导体衬底上，源极电连接到源极结并形成在沟槽中的缓冲介电膜之间; 以及形成在除了沟槽之外的半导体衬底的表面上的漏极结。版权所有（C）2006，JPO＆NCIPI

56. 发明专利

JP2006135319A Hetero integration type strained silicon n-type mosfet, p-type mosfet, and method of manufacturing the same 有权
标题翻译：异质集成型应变硅N型MOSFET，P型MOSFET及其制造方法
公开(公告)号：JP2006135319A
公开(公告)日：2006-05-25
申请号：JP2005309279
申请日：2005-10-25
申请人： Internatl Business Mach Corp , インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation
发明人： DAINE C BOYD , CAI JUAN , KEVIN K CHAN , MOONEY PATRICIA M , KERN LIM
IPC分类号： H01L21/20 , H01L21/265 , H01L21/8238 , H01L27/092 , H01L29/78
CPC分类号： H01L29/1054 , H01L21/02378 , H01L21/02381 , H01L21/02532 , H01L21/02664 , H01L21/26506 , H01L21/26513 , H01L21/823807 , H01L29/7842 , Y10S438/938
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor structure for use in n-type and p-type MOSFET devices, and the method of manufacturing the same.
SOLUTION: A semiconductor structure is formed such that the layer structure of a wafer region by which an n-type MOSFET is manufactured is different from the layer structure of a wafer region by which a p-type MOSFET is manufactured. First, the structure is manufactured by forming a damage region on the front surface of an Si content substrate by ion implantation of a light atom such as He. Then, strained SiGe alloy is formed on the Si content substrate comprising the damage region. Then, the strained SiGe alloy is made to ease substantially by strained relaxation resulting from defect using an anneal step. Then, a strained semiconductor cap of strained Si etc. is formed on the strained SiGe alloy.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供用于n型和p型MOSFET器件的半导体结构及其制造方法。解决方案：形成半导体结构，使得制造n型MOSFET的晶片区域的层结构不同于制造p型MOSFET的晶片区域的层结构。首先，通过用诸如He的光原子的离子注入在Si含量衬底的前表面上形成损伤区域来制造结构。然后，在包含损伤区域的Si含量基板上形成应变SiGe合金。然后，使应变SiGe合金基本上通过使用退火步骤的缺陷导致的应变弛豫来简化。然后，在应变SiGe合金上形成应变Si等的应变半导体盖。版权所有（C）2006，JPO＆NCIPI

57. 发明专利

JP2004179670A Manufacturing of insulating film layer isolation ic 审中-公开
公开(公告)号：JP2004179670A
公开(公告)日：2004-06-24
申请号：JP2003411689
申请日：2003-12-10
申请人： Glenn J Leedy , リーディ,グレン・ジェイ
发明人： LEEDY GLENN J
IPC分类号： G21K5/02 , B81B3/00 , G02F1/13 , G03F7/20 , G11C29/00 , H01L21/027 , H01L21/306 , H01L21/331 , H01L21/336 , H01L21/76 , H01L21/762 , H01L21/764 , H01L21/822 , H01L21/8234 , H01L21/8238 , H01L21/98 , H01L23/48 , H01L23/538 , H01L25/065 , H01L27/00 , H01L27/02 , H01L27/08 , H01L27/088 , H01L27/092 , H01L27/12 , H01L29/732 , H01L29/78 , H01L29/786 , H05G1/00
CPC分类号： H01L25/50 , G02F1/13452 , G02F2001/136281 , G03F7/70658 , G11C29/006 , H01L21/762 , H01L21/76264 , H01L21/76289 , H01L21/764 , H01L21/8221 , H01L23/481 , H01L23/538 , H01L23/5381 , H01L23/5383 , H01L23/5386 , H01L23/5387 , H01L25/0652 , H01L25/0655 , H01L27/0207 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/16225 , H01L2224/16227 , H01L2924/00011 , H01L2924/0002 , H01L2924/01014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15312 , H01L2924/3011 , H01L2924/3025 , Y10S148/135 , Y10S438/928 , Y10S438/938 , Y10S438/942 , Y10S438/967 , Y10S438/977 , Y10T29/49128 , Y10T29/49162 , Y10T29/49165 , Y10T29/49171 , Y10T29/4921 , H01L2924/00 , H01L2224/05552 , H01L2224/80001
摘要： PROBLEM TO BE SOLVED: To provide a versatile method for manufacturing an integrated circuit by a flexible film formed by an extremely thin stress reducing dielectric material such as silicon dioxide and silicon nitride and a semiconductor layer. SOLUTION: Semiconductor devices (24, 26, 28 to 30) are formed in a semiconductor layer of a film (36). At first, the semiconductor film layer (36) is formed from a substrate (18) of standard thickness, and next, a thin surface layer of the substrate is etched or polished. In other version, a support for the conventional bonding integrated circuit die and a flexible film as electrically mutual connection are used, and a mutual connection part is formed in a plurality of layers in the film. By this method, a plurality of dies can be connected to one of the films, and the film is subsequently packaged as a multi-chip module. COPYRIGHT: (C)2004,JPO

58. 发明专利

JP3500541B2 Method of manufacturing a single-electron tunnel junction devices 失效
公开(公告)号：JP3500541B2
公开(公告)日：2004-02-23
申请号：JP1797794
申请日：1994-02-15
申请人：富士通株式会社
发明人：アーサーキールリチャード
IPC分类号： H01L29/66 , H01L29/06 , H01L29/10 , H01L29/12 , H01L29/15 , H01L29/76 , H01L29/88 , H01L31/0352
CPC分类号： B82Y10/00 , H01L29/1075 , H01L29/127 , H01L29/155 , H01L29/7613 , H01L31/0352 , Y10S438/938

59. 发明专利

JPS597210B2 JPS597210B2 - 失效
公开(公告)号：JPS597210B2
公开(公告)日：1984-02-17
申请号：JP12961674
申请日：1974-11-12
申请人： Western Electric Co
发明人： PIEERU MARUKU PETOROFU , JOOJI AASAA ROGONII
IPC分类号： H01L21/208 , H01L33/00 , H01S5/00 , H01S5/20 , H01S5/223 , H01S5/32 , H01S5/323
CPC分类号： H01S5/32308 , H01L33/0025 , H01S5/20 , H01S5/2059 , H01S5/223 , H01S5/3211 , Y10S148/065 , Y10S148/066 , Y10S148/067 , Y10S148/097 , Y10S148/107 , Y10S438/938

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