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51. 发明专利

JP2002150780A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2002150780A
公开(公告)日：2002-05-24
申请号：JP2000342171
申请日：2000-11-09
申请人： TOSHIBA CORP
发明人： KAWAI KOICHI , IMAMIYA KENICHI , HIMENO TOSHIHIKO
IPC分类号： G11C16/02 , H03K19/096
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which can perform surely reset operation without complexing a circuit configuration. SOLUTION: This device is provided with an integrated circuit section 20, a time prescribing circuit 21 prescribing an operation time of this integrated circuit section, a time changing circuit 22 being one or more which changes all or one part of an operation time prescribed by the time prescribing circuit 21, and a state transition control circuit 23 which is started in accordance with a first input (data write-in signal), controls a series of state transition from an initial state of the integrated circuit section 20 to returning to this initial state in accordance with an operation tiome prescribed the time prescribing circuit 21, while controls state transition after this second input is inputted in accordance with a time changed by the time changing circuit 22 even from the midst of a series of state transition and in accordance with a second input (non-synchronism reset).

52. 发明专利

JP2001312890A NON-VOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JP2001312890A
公开(公告)日：2001-11-09
申请号：JP2000127950
申请日：2000-04-27
申请人： TOSHIBA CORP
发明人： IKEHASHI TAMIO , IMAMIYA KENICHI
IPC分类号： G11C16/02 , G11C16/04 , G11C16/34
摘要： PROBLEM TO BE SOLVED: To perform accurately discrimination of data in verify-read. SOLUTION: One page buffer P/B is connected to one bit line. Each pace buffer P/B latches program data for a selected memory cell. Plural page buffers P/B are connected to a sense amplifier S/A.0 in a read-out/write-in circuit through a column gate. In verify-read, detection of read-data of a selected column is performed by using the sense amplifier for normal data-read. Read- data detected by the sense amplifier S/A.0, that is, a result of verify-read is transferred to a page buffer P/B of a selected column. Program data in the page buffer P/B is rewritten based on this result of verify-read.

53. 发明专利

JP2001184881A READ-OUT CIRCUIT FOR NON-VOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JP2001184881A
公开(公告)日：2001-07-06
申请号：JP37306999
申请日：1999-12-28
申请人： TOSHIBA CORP
发明人： IKEHASHI TAMIO , IMAMIYA KENICHI , NODA JUNICHIRO
IPC分类号： G11C16/06 , G11C7/06 , G11C8/02 , G11C16/28
摘要： PROBLEM TO BE SOLVED: To realize read-out operation at high speed and with low power consumption. SOLUTION: An INVSRC node 31 and a SAREF node 32 are previously charged. After a potential of a bit line BLj is reset, the bit line BLj (BLS node 34) is pre-charged. At that time, MOS transistors M11, M12 are in an ON state, a SA node also is simultaneously pre-charged. A pre-charge level is set to a lower value than threshold voltage Vsense of an inverter INV1. After that, when SAEN is made 'H', sense operation is performed. When '0' is read out, the SA node 33 is raised to Vdd quickly. When '1' is read out, the SA node 33 approaches to Vss slowly. Potential variation of the SA node 33 is detected by the inverter INV1.

54. 发明专利

JP2001143488A SEMICONDUCTOR MEMORY, DATA READ-OUT METHOD THEREFOR, AND SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JP2001143488A
公开(公告)日：2001-05-25
申请号：JP32548099
申请日：1999-11-16
申请人： TOSHIBA CORP
发明人： IMAMIYA KENICHI
IPC分类号： G11C11/417 , G11C11/419 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory and a semiconductor integrated circuit device, in which power consumption at the time of read-out of data can be reduced. SOLUTION: This device has a memory cell array 2 having plural memory cells 1, a row address decoder 3 controlling the voltage of a word line, column decoder 4 controlling the voltage of a column line, sense amplifier 5 amplifying data read out of a specific memory cell 1, latch circuit 6 latching the output of the sense amplifier 5, and output buffer 7 buffering the output of the latch circuit 6 and supplying it to a data output terminal. Since the latch circuit 6 is provided between the sense amplifier 5 and the output buffer 7, after the output of the sense amplifier 5 is latched by the latch circuit 6, a latch output of the latch circuit 6 is transmitted to the output buffer 7, after the latch by the latch circuit 6, even if sense operation of the sense amplifier 5 is stopped, data read out from a memory can be outputted normally.

55. 发明专利

JP2000194598A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2000194598A
公开(公告)日：2000-07-14
申请号：JP36927998
申请日：1998-12-25
申请人： TOSHIBA CORP
发明人： OHIRA HIDEKO , IMAMIYA KENICHI , SUGIURA YOSHIHISA
IPC分类号： G11C16/02 , G06F12/06
摘要： PROBLEM TO BE SOLVED: To easily output a set identification signal by providing a setting means for setting the identification signal for identifying a semiconductor chip and a transfer circuit which has one end connected to the setting means and the other end connected to a pad through a buffer circuit and transfers the output signal of the setting means. SOLUTION: Input terminals of output buffers 31a to 31h are connected to one-end sides of transfer gates 33a to 33h. An identification signal setting circuit 38 is connected to the other-end sides of the transfer gates 33a and 33b. A source voltage Vcc or ground potential Vss is supplied to the other-end sides of the transfer gates 33c to 33h. The level of the power supplied to the other-end sides of those transfer gates 33a to 33h is set according to an identification signal indicating the storage capacity of the chip or an identification signal indicating the storage capacity of SSFDC. The identification signals are switched by varying the potential of, for example, low-order two bits. The potential of the low-order two bits is set by using an identification signal setting circuit 38 connected to an option pad.

56. 发明专利

JP2000150789A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JP2000150789A
公开(公告)日：2000-05-30
申请号：JP31916198
申请日：1998-11-10
申请人： TOSHIBA CORP
发明人： IMAMIYA KENICHI , IKEHASHI TAMIO
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L27/06
摘要： PROBLEM TO BE SOLVED: To increase the capacitance of a capacitor without increasing the element area of the capacitor. SOLUTION: A capacitor is provided with a pair of N-type semiconductor areas 27 and 28 provided in the surface area of a semiconductor substrate 20, an electrode 31 provided on a channel area 29 between the areas 27 and 28 through an insulating film 30, and another electrode 33 provided on the electrode 31 through another insulating film 32. The semiconductor areas 27 and 28 are electrically connected to the electrode 33 and the common connection node of the electrode 33 is used as one electrode T1 of the capacitor. The electrode 31 is used as the other electrode T2 of the capacitor.

57. 发明专利

JP2000091546A NON-VOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JP2000091546A
公开(公告)日：2000-03-31
申请号：JP25877898
申请日：1998-09-11
申请人： TOSHIBA CORP
发明人： NAKAMURA HIROSHI , OHIRA HIDEKO , IMAMIYA KENICHI , TAKEUCHI TAKESHI , ARITOME SEIICHI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To avoid the erroneous read out due to capacitance coupling between wirings. SOLUTION: Seledive gate lines (149) are respectively arranged in BLOCK i-1, BLOCK i. In a shunt region QQ, contact part X1 with the selective gate lines (149) in the BLOCK i-1 is provided. A selective gate bypath 21i-1 connecting to the selective gate lines (149) is arranged in the BLOCKi adjacent to the BLOCK i-1.

58. 发明专利

JPH113934A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH113934A
公开(公告)日：1999-01-06
申请号：JP15358497
申请日：1997-06-11
申请人： TOSHIBA CORP
发明人： IMAMIYA KENICHI , NAKAMURA HIROSHI
IPC分类号： H01L21/76 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit, wherein isolation between transistors can be surely executed by a shield wiring layer (shield poly) provided to an isolation region, freedom of pattern layout can be increased, and a chip area required for pattern layout can be reduced. SOLUTION: Electric field generated from a wiring layer 9 is shielded by setting an electric potential of a shield wiring layer 7 provided on a field oxide film at a fixed electric potential (source voltage Vcc) which is not equal to the electric potential of a board or a well but different therefrom and by biasing a variable electric potential which becomes an electric potential whereat a parasitic MOS transistor formed in the field oxide film part does not turn 'on' when MIS transistors M1, M2 differ in electric potential to the shield wiring layer 7.

59. 发明专利

JPH02223096A NONVOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH02223096A
公开(公告)日：1990-09-05
申请号：JP4350189
申请日：1989-02-23
申请人： TOSHIBA CORP
发明人： OTSUKA NOBUAKI , MIYAMOTO JUNICHI , TANAKA SUMIO , IMAMIYA KENICHI
IPC分类号： G11C17/00 , G11C16/04 , G11C16/06 , G11C29/00 , G11C29/24
摘要： PURPOSE:To prevent write to a dummy memory cell by providing a transistor (TR) whose one terminal is connected to a reference level and whose other terminal is connected to a dummy bit line and which is conducted in the operating mode period when all plural word lines are brought into the selective state. CONSTITUTION:A TR 21 connected to a dummy bit line DBL is conductive by a control signal MOD in the test mode. Thus, the level of all word lines WL1-WLn rises simultaneously to a high level Vpp, the dummy bit line DBL is booted by the capacitive coupling by a parasitic capacity between a gate and a drain of each 1st dummy memory cell and between the gate and a channel, and even when the level rises to a high level, the level is discharged via the conductive TR 21 and the level of the dummy bit line DBL is immediately lowered. Thus, the write to the dummy memory cell is prevented.

60. 发明专利

JPH0225775A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0225775A
公开(公告)日：1990-01-29
申请号：JP17672188
申请日：1988-07-15
申请人： TOSHIBA CORP
发明人： ATSUMI SHIGERU , TANAKA SUMIO , MIYAMOTO JUNICHI , OTSUKA NOBUAKI , IMAMIYA KENICHI
IPC分类号： G01R31/28 , G01R31/3185 , G11C11/401 , G11C11/409 , H01L21/66
摘要： PURPOSE:To allow operating speed to be low and to suppress the generation of a noise by lowering the driving ability of a pre-buffer circuit or an output buffer circuit at the time of a test mode. CONSTITUTION:Pre-buffer circuits 20 and 30 to be composed of CMOS inverters 21, 26, 31 and 36 are connected to an output buffer circuit 10 and by wafer test signals WT, the driving of the inverters 26 and 36 is controlled. Then, the driving ability to the output buffer circuit 10 is lowered. Otherwise, the output buffer circuit 10 is composed of two types of PMOS and NMOS transistors 14-17 and the output buffer circuit 10 is controlled through gates 27 and 37 by the wafer test signals WT. Then, the driving ability to the load of the output buffer circuit 10 is lowered. Thus, at the time of a wafer test, the operating speed of the output buffer circuit is made low and the noise can be prevented from being generated by the output buffer.

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