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    • 52. 发明专利
    • CLOCK REPRODUCTION CIRCUIT
    • JPH10126401A
    • 1998-05-15
    • JP29590196
    • 1996-10-18
    • MATSUSHITA ELECTRIC IND CO LTD
    • NAKAJIMA TAKESHI
    • H03L7/06H04B7/26H04L7/033H04L7/08
    • PROBLEM TO BE SOLVED: To inexpensively and fast correct a frequency of a reproduction clock by setting learning data at the time of convergence to the optimum value that is held in memory when learning data makes a big error, etc. SOLUTION: When a voltage on-detecting circuit 12 detects a PONRST signal, it outputs a voltage on-detection signal 20 to a control circuit 18 and the circuit 18 reads learning data at the time of convergence to the optimum value that is stored in memory 19 and sets it to a learning correction functional digital PLL 17. When an LVA signal (active L) is received, learning data 26 of the circuit 18 is cleared and at this moment, the memory 19 stores the learning data at the time of convergence to the optimum value. There, a hit return signal 22 from a hit detection circuit 13 is outputted, a receiving mode is switched from intermittent receiving to continuous receiving, and the circuit 18 reads the learning data at the time of convergence to the optimum value from the memory 19 with the tailing edge of the signal 22 and sets it to the PLL 17.
    • 53. 发明专利
    • DIGITAL PLL
    • JPH09312564A
    • 1997-12-02
    • JP12464596
    • 1996-05-20
    • MATSUSHITA ELECTRIC IND CO LTD
    • NAKAJIMA TAKESHIABE MITSUHARU
    • H03L7/06H04J3/06H04L7/033H04L27/22
    • PROBLEM TO BE SOLVED: To correct frequency difference due to the stability deterioration of TCXO during a non-reception period by information of difference between a reproducing clock obtained during the reception period and a base station transmitting clock with respect to the digital PLL which generates the reproducing clock of a TDMA system movement machine. SOLUTION: Phase following is executed in order to hold synchronization with a base station by clock reference 29 which is generated by a receiving signal (IF) in the digital PLL 14, a detecting circuit 15 detects a frequency dividing variable signal, an up-down control signal 23 with a load value N is operated based on an enable signal 22 and an up-down control signal 23 and the up-down counter B17 is operated by an outputted overflow signal 24 and the up-down control signal 25. The output of the up-down counter B17 is integrated by an integrating equipment 18 by a symbol unit so that frequency difference due to the stability deterioration of TCXO by information of difference between the reproducing clock obtained during the reception period and the base station transmitting clock is corrected and synchronization with the base station is held.
    • 54. 发明专利
    • TRANSMISSION/RECEPTION DATA CONTROLLER
    • JPH09148982A
    • 1997-06-06
    • JP32619495
    • 1995-11-22
    • MATSUSHITA ELECTRIC IND CO LTD
    • NAKAJIMA TAKESHI
    • H04J3/06H04B7/26H04L7/08
    • PROBLEM TO BE SOLVED: To realize stable communication by controlling transmission with the free-running timer of one slave machine which is designated to be a temporary master at the time of direct communication between the slave machines. SOLUTION: At the time of direct communication between the slave machines, a call-side slave machine is designated to be the temporary master, for example, and the designation and a reproduction clock are synchronized with a reproduction clock fall by the edge detection circuit of the free-running timer 15. The enable of a frequency divider 14 is set to be high. The frequency divider 14 generates a free-running clock 1 based on a transmitter clocks signal, frequency- divides it into 1/2 and generates a self-running clock 2. The counter value of a timer 13 at that time is succeeded and it is loaded on the counter of the timer 15 with the clock 2. It counts it up based on the clock 2 and outputs it, Thus, self slot transmission timing on an air interface can be generated. Thus, transmission control is executed at the absolute time of the timer 15 and a transmission/reception processing on the air interface can be executed within the self slot. Then, collision with the other slot is eliminated and stable inter-slave machine direct communication can be realized.